1. PowerBench Programmable Power Supply Dror Lazar Moran Fishman Supervisor: Boaz Mizrahi Winter Semester 2009/10 HS DSL

2. Presentation Contents  Project overview - Reminder  Current Status (What have been done)  What’s left

3. Project Overview - Reminder A versatile power supply unit with multiple outputs for laboratory use and testing of various electronic devices.

4. Active load Power supply Control unit User interface for standalone operation LCDKeysLEDs User interface DUTDUT Measurement unit ססס A brief reminder Project Overview - Reminder

5. DC-DC Converter Post regulator ADC Voltage Sense DAC Current Sense Output FPGA Controller Block & Registers Output setting Input voltage sense feed- forward Tempe- rature Current limit PWM Microprocessor Overview – Control Scheme ADC Auxiliary Voltage Sense

6. Current Status  FPGA design  Analog board bring-up  PC – FPGA communication

7. FPGA Design

8.  Clocks & buffers : DCMs - internal clocks generation IDDRs - sampling 2-channel A/Ds ODDRs – clocks output to peripherals Reset synchronization  Analog board interfaces : 1x 4-channel A/D (sampling buck/cuk outputs) 2x 2-channel A/D (sampling sensed current & voltages) 2x DAC (to LDOs and active load circuits) 3x PWM (to buck converters)

9. FPGA Design  Cypress FX2 interface FX2 signals logic High bandwidth data FIFO buffer  PIC microcontroller interface Register bank Data DPRs (with FIFO interface to PIC) SPI interface : physical & data link layers  FPGA design Documentation : Registers, operation modes, PIC interface, FX2 interface

10. Analog board bring-up  Chip/Circuit Validation : 1x 4-channel A/D 2x DAC 3x Buck converter

11. PC – FPGA communication  PIC software : SPI module (PIC – FPGA) PMP module (PIC – FX2) FPGA soft-reset module  FX2 software : PC enumeration (done by Greg) End-Points configuration Slave-FIFO configuration  Configure FPGA registers using PC : PC => FX2 => PIC => FPGA => PIC => FX2 => PC

12. What’s Left  FPGA Design : Learn about SMPS digital control techniques Implement & simulate buck regulator controller (x4) Implement Cuk converter interface  FX2 software : Slave-FIFO interface change by PIC command (using INT)  PIC software : Configure FPGA and FX2 to ‘Sensing mode’ and back Burn FPGA’s FLASH (using SPI) by PC command

13. What’s Left  PC software : Learn C++ Implement FPGA bit-stream download to on-board FLASH  Analog board bring-up : Cuk converter debug and validation LDO circuit debug and validation Active-load circuit debug and validation Sense A/Ds validation Buck regulator validation

14. Questions ?