1. ECE/CS 352 Digital System Fundamentals© T. Kaminski & C. Kime 1 ECE/CS 352 Digital Systems Fundamentals Spring 2001 Chapter 4 – Part 4 Tom Kaminski & Charles R. Kime

2. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 2 Overview of Chapter 4 Types of Sequential Circuits Storage Elements –Latches –Flip-Flops Sequential Circuit Analysis –State Tables –State Diagrams Sequential Circuit Design –Specification –Assignment of State Codes –Implementation –HDL Representation

3. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 3 Developing the State Diagram

4. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 4 Developing the State Diagram

5. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 5 Sequence Recognizer Procedure

6. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 6 Sequence Recognizer Example

7. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 7 Example: Recognize 1101

8. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 8 Recognize 1101 (Continued)

9. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 9 Recognize 1101 (Continued)

10. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 10 Recognize 1101 (Continued)

11. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 11 Complete the Diagram (1101)

12. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 12 Add Missing Arcs

13. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 13 1101 State Table from Diagram From State A, the “0” and “1” input transitions have been filled in along with the outputs.

14. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 14 Complete 1101 State Table

15. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 15 Moore Model for 1101

16. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 16 Moore Diagram for 1101

17. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 17 Moore State Table for 1101

18. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 18 Second State Diagram Example A register consists of an ordered set of n flip-flops plus combinational logic to determine its next state. If a register can be designed as a set of n identical cells, the register cell can be designed as a two-state sequential circuit. Next we will consider such as example.

19. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 19 Register Specification Diagram: Table: Parallel Load Register with Synchronous Clear and Load OperationCLSLDSResult (Next State) Hold Reg00Data_out Load Reg01Data_in Clear Reg1-0000000 CLS LDS CLK Data_in (7:0) Data_out(7:0) Register(7:0) RESET (Async)

20. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 20 Second Example: Register Cell Design By definition, a register cell is a sequential circuit that:  contains one flip-flop (2 states)  has the flip-flop output as the primary external register output (Moore model) Cell Diagram: CLS LDS CLK Data_in (i) Data_out(i) Reg. Cell(i) RESET (Async) FF

21. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 21 Initial State: Add Load: Add Clear: Second Example: State Diagram Design A/0 RESET A/0 RESET CLS,LDS,Data_in A/0 RESET B/1 1, 1 1, 0 B/1 0, 1, 1 0, 1, 0; 1, -, - LDS,Data_in 0,1,0; 1,-,- 1, 1 1, 0 State/Data_out(i) 0,1,1 State/Data_out(i)

22. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 22 Make the state unchanged (Hold Reg) by adding all unused input combinations for each state. Second Example: State Diagram Design A/0 RESET CLS,LDS,Data_in B/1 0, 1, 1 0, 1, 0; 1, -, - 0,1,0; 1,-,-; 0,0,- State/Data_out(i) 0,1,1; 0,0,-

23. ECE/CS 352 Digital System Fundamentals Chapter 4 Page 23 Second Example: State Table From State Diagram: CLS, LDS, Data_in Input: State: 000001010011100101110111Output AAAABAAAA0 BBBABAAAA1