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Introduction to Computing Systems and Programming Digital Logic Structures.

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1 Introduction to Computing Systems and Programming Digital Logic Structures

2 Fall 1384, 2Introduction to Computing Systems and Programming Logical Operations  0, 1 in a binary value can represent logical TRUE = 1, or FALSE = 0.  We can perform logical operations on binary bits or a set of binary bits, also known as Boolean algebra.  The basic operations are AND, OR, NOT

3 Fall 1384, 3Introduction to Computing Systems and Programming Basic Logic Operations Truth Tables of Basic Operations Equivalent Notations Not A = A’ = A A and B = A.B = A  B = A intersection B A or B = A+B = A  B = A union B AND ABA.BA.B 000 010 100 111 OR ABA+BA+B 000 011 101 111 NOT AA' 01 10

4 Fall 1384, 4Introduction to Computing Systems and Programming More Logic Operations  XOR and XNOR XOR AB ABAB 000 011 101 110 XNOR AB (A  B)’ 001 010 100 111

5 Fall 1384, 5Introduction to Computing Systems and Programming Logical Operations Example  AND useful for clearing bits AND with zero = 0 AND with one = no change  OR useful for setting bits OR with zero = no change OR with one = 1  NOT unary operation -- one argument flips every bit 11000101 AND 00001111 00000101 11000101 OR 00001111 11001111 NOT 11000101 00111010

6 Fall 1384, 6Introduction to Computing Systems and Programming Simple Switch Circuit Switch open: Switch open: –No current through circuit –Light is off –V out is +2.9V Switch closed: Switch closed: –Short circuit across switch –Current flows –Light is on –V out is 0V Switch-based circuits can easily represent two states: on/off, open/closed, voltage/no voltage.

7 Fall 1384, 7Introduction to Computing Systems and Programming Transistor  Microprocessors contain millions of transistors Intel Pentium II: 7 million Intel Pentium III: 28 million Intel Pentium 4: 54 million  Logically, each transistor acts as a switch

8 Fall 1384, 8Introduction to Computing Systems and Programming N-type MOS Transistor Gate = 1 Gate = 0 Terminal #2 must be connected to GND (0V). MOS = Metal Oxide Semiconductor MOS = Metal Oxide Semiconductor –two types: N-type and P-type N-type N-type –when Gate has positive voltage, short circuit between #1 and #2 (switch closed) –when Gate has zero voltage, open circuit between #1 and #2 (switch open)

9 Fall 1384, 9Introduction to Computing Systems and Programming P-type MOS Transistor  P-type is complementary to N-type when Gate has positive voltage, open circuit between #1 and #2 (switch open) when Gate has zero voltage, short circuit between #1 and #2 (switch closed) Gate = 1 Gate = 0 Terminal #1 must be connected to +2.9V.

10 Fall 1384, 10Introduction to Computing Systems and Programming CMOS Circuit  Complementary MOS  Uses both N-type and P-type MOS transistors P-type Attached to + voltage Pulls output voltage UP when input is zero N-type Attached to GND Pulls output voltage DOWN when input is one  For all inputs, make sure that output is either connected to GND or to +, but not both!

11 Fall 1384, 11Introduction to Computing Systems and Programming Inverter (NOT Gate) InOut 0 V2.9 V 0 V InOut 01 10 Truth table

12 Fall 1384, 12Introduction to Computing Systems and Programming NOR Gate ABC 001 010 100 110 C A B 2.9 v 0 v P N P N

13 Fall 1384, 13Introduction to Computing Systems and Programming NOR Gate Operation 2.9 v 0 v P N P 2.9 v 0 v N P N 2.9 v 0 v N P N P N 2.9 v 0 v P

14 Fall 1384, 14Introduction to Computing Systems and Programming OR Gate Add inverter to NOR. ABC 000 011 101 111

15 Fall 1384, 15Introduction to Computing Systems and Programming NAND Gate (AND-NOT) ABC 001 011 101 110

16 Fall 1384, 16Introduction to Computing Systems and Programming AND Gate Add inverter to NAND. ABC 000 010 100 111

17 Fall 1384, 17Introduction to Computing Systems and Programming Basic Logic Gates

18 Fall 1384, 18Introduction to Computing Systems and Programming More Inputs  AND/OR can take any number of inputs. AND = 1 if all inputs are 1. OR = 1 if any input is 1. Similar for NAND/NOR.  Can implement with multiple two-input gates, or with single CMOS circuit.

19 Fall 1384, 19Introduction to Computing Systems and Programming Logical Completeness  Can implement ANY truth table with AND, OR, NOT. ABCD 0000 0010 0101 0110 1000 1011 1100 1110 1. AND combinations that yield a "1" in the truth table. 2. OR the results of the AND gates.

20 Fall 1384, 20Introduction to Computing Systems and Programming Practice  Implement the following truth table. ABC 000 011 101 110 ABC 001 010 100 111

21 Fall 1384, 21Introduction to Computing Systems and Programming Summary  MOS transistors are used as switches to implement logic functions. N-type: connect to GND, turn on (with 1) to pull down to 0 P-type: connect to +2.9V, turn on (with 0) to pull up to 1  Basic gates: NOT, NOR, NAND Logic functions are usually expressed with AND, OR, and NOT  Properties of logic gates Completeness can implement any truth table with AND, OR, NOT DeMorgan's Law convert AND to OR by inverting inputs and output

22 Fall 1384, 22Introduction to Computing Systems and Programming Logic Structures  We've already seen how to implement truth tables using AND, OR, and NOT -- an example of combinational logic.  Combinational Logic Circuit output depends only on the current inputs stateless  Sequential Logic Circuit output depends on the sequence of inputs (past and present) stores information (state) from past inputs

23 Fall 1384, 23Introduction to Computing Systems and Programming Decoder  n inputs, 2 n outputs exactly one output is 1 for each possible input pattern 1, iff A,B is 00 A B 1, iff A,B is 01 1, iff A,B is 10 1, iff A,B is 11 i = 0 i = 1 i = 2 i = 3

24 Fall 1384, 24Introduction to Computing Systems and Programming Multiplexer  n-bit selector and 2 n inputs, one output output equals one of the inputs, depending on selector 4-to-1 MUX

25 Fall 1384, 25Introduction to Computing Systems and Programming Half Adder  Half Adder 2 inputs 2 outputs: sum and carry

26 Fall 1384, 26Introduction to Computing Systems and Programming Full Adder  Add two bits and carry-in, produce one-bit sum and carry-out. ABC in SC out 00000 00110 01010 01101 10010 10101 11001 11111

27 Fall 1384, 27Introduction to Computing Systems and Programming Four-bit Adder

28 Fall 1384, 28Introduction to Computing Systems and Programming Combinational vs. Sequential  Combinational Circuit always gives the same output for a given set of inputs ex: adder always generates sum and carry, regardless of previous inputs  Sequential Circuit stores information output depends on stored information (state) plus input so a given input might produce different outputs, depending on the stored information example: ticket counter advances when you push the button output depends on previous state useful for building “memory” elements and “state machines”

29 Fall 1384, 29Introduction to Computing Systems and Programming R-S Latch  If both R and S are one, out could be either zero or one. “quiescent” state -- holds its previous value note: if a is 1, b is 0, and vice versa 1 0 1 1 1 1 0 0 1 1 0 0 1 1

30 Fall 1384, 30Introduction to Computing Systems and Programming Clearing the R-S latch  Suppose we start with output = 1, then change R to zero. Output changes to zero. 1 0 1 1 1 1 0 0 1 0 1 0 0 0 1 1

31 Fall 1384, 31Introduction to Computing Systems and Programming Setting the R-S Latch  Suppose we start with output = 0, then change S to zero. Output changes to one. 1 1 0 0 1 1 0 1 1 1 0 0

32 Fall 1384, 32Introduction to Computing Systems and Programming R-S Latch  R = S = 1 hold current value in latch  S = 0, R=1 set value to 1  R = 0, S = 1 set value to 0  R = S = 0 both outputs equal one final state determined by electrical properties of gates Don’t do it!

33 Fall 1384, 33Introduction to Computing Systems and Programming Gated D-Latch  Two inputs: D (data) and WE (write enable) when WE = 1, latch is set to value of D S = NOT(D), R = D when WE = 0, latch holds previous value S = R = 1

34 Fall 1384, 34Introduction to Computing Systems and Programming Register  A register stores a multi-bit value. We use a collection of D-latches, all controlled by a common WE. When WE=1, n-bit value D is written to register.

35 Fall 1384, 35Introduction to Computing Systems and Programming Memory  Now that we know how to store bits, we can build a memory – a logical k × m array of stored bits. k = 2 n locations m bits Address Space: number of locations (usually a power of 2) Addressability: number of bits per location (e.g., byte-addressable)

36 Fall 1384, 36Introduction to Computing Systems and Programming Address Space  n bits allow the addressing of 2 n memory locations. Example: 24 bits can address 2 24 = 16,777,216 locations (i.e. 16M locations). If each location holds 1 byte then the memory is 16MB. If each location holds one word (32 bits = 4 bytes) then it is 64 MB.

37 Fall 1384, 37Introduction to Computing Systems and Programming Addressability  Computers are either byte or word addressable - i.e. each memory location holds either 8 bits (1 byte), or a full standard word for that computer (typically 32 bits, though now many machines use 64 bit words).  Normally, a whole word is written and read at a time: If the computer is word addressable, this is simply a single address location. If the computer is byte addressable, and uses a multi-byte word, then the word address is conventionally either that of its most significant byte (big endian machines) or of its least significant byte (little endian machines).

38 Fall 1384, 38Introduction to Computing Systems and Programming Memory Structure  Each bit is a gated D-latch  Each location consists of w bits (here w = 1) w = 8 if the memory is byte addressable  Addressing n locations means log 2 n address bits (here 2 bits => 4 locations) decoder circuit translates address into 1 of n addresses WE A[1:0] D

39 Fall 1384, 39Introduction to Computing Systems and Programming 2 2 by 3 bits memory: A 2 2 by 3 bits memory: two address lines: A[1:0]two address lines: A[1:0] three data lines: D[2:0]three data lines: D[2:0] one control line: WEone control line: WE One gated D-latch Memory example

40 Fall 1384, 40Introduction to Computing Systems and Programming 2 2 x 3 Memory address decoder word select word WE address write enable input bits output bits

41 Fall 1384, 41Introduction to Computing Systems and Programming Memory details  This is a not the way actual memory is implemented. fewer transistors, much more dense, relies on electrical properties  But the logical structure is very similar. address decoder word select line word write enable  Two basic kinds of RAM (Random Access Memory)  Static RAM (SRAM) fast, maintains data without power  Dynamic RAM (DRAM) slower but denser, bit storage must be periodically refreshed

42 Fall 1384, 42Introduction to Computing Systems and Programming Memory building blocks –Building an 8K byte memory using chips that are 2K by 4 bits. CS = chip select: when set, it enables the addressing, reading and writing of that chip. This is an 8KB byte addressable memory d e c o d er CS A10-A0 A12-A11 2K x 4 bits

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