1. FPGA: Field Programmable Gate Array
Yann-Hang Lee
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2. The Next Step of PAL
So far, have only talked about PALs (see 22V10 figure next page).
What is the next step in the evolution of PLDs?
More gates!
How do we get more gates? We could put several PALs on one chip and put an interconnection matrix between them!!
This is called a Complex PLD (CPLD).
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3. Example: 22V10 PLD
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4. Programmable interconnect matrix.
Cypress CPLD
Each logic block is similar to a 22V10.
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5. Any other approaches?
Another approach to building a “better” PLD is place a lot of primitive gates on a die, and then place programmable interconnect between them:
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6. Field Programmable Gate Arrays
The FPGA approach to arrange primitive logic elements (logic cells) arrange in rows/columns with programmable routing between them.
What constitutes a primitive logic element? Lots of different choices can be made! Primitive element must be classified as a “complete logic family”.
A primitive gate like a NAND gate
A 2/1 mux (this happens to be a complete logic family)
A Lookup table (I.e, 16x1 lookup table can implement any 4 input logic function).
Often combine one of the above with a D-FF to form the primitive logic element.
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7. Altera Flex 10K FPGA Family
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8. Dedicated memory
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9. What is FPGA Field Programmable Gate Arrays
Array of logic cells connected via routing channels
Special I/O cells
logic cells are mainly LUT with associated registers
interconnection on SRAM basis or antifuse elements
Architecting a FPGA
Performance
Density and capacity
Ease of use
In-system programmability and in-circuit reprogrammability
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10. Technology and Architecture Tradeoffs
Antifuse elements
high density
non volatile
not reprogrammable
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11. Technology and Architecture Tradeoffs
SRAM cells
uses more space
reconfigurable
volatile, requires PROM
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12. Other FPGA features
Besides primitive logic elements and programmable routing, some FPGA families add other features
Embedded memory
Many hardware applications need memory for data storage. Many FPGAs include blocks of RAM for this purpose
Dedicated logic for carry generation, or other arithmetic functions
Phase locked loops for clock synchronization, division, multiplication.
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13. Programmable Logic Device Families
Source: Dataquest
Logic
Standard
ASIC
Programmable
Logic Devices
(PLDs)
Gate
Arrays
Cell-Based
ICs
Full Custom
CPLDs
SPLDs
(PALs)
FPGAs
Common Resources
Configurable Logic Blocks (CLB)
Memory Look-Up Table
AND-OR planes
Simple gates
Input / Output Blocks (IOB)
Bidirectional, latches, inverters, pullup/pulldowns
Interconnect or Routing
Local, internal feedback, and global
Acronyms
SPLD = Simple Prog. Logic Device
PAL = Prog. Array of Logic
CPLD = Complex PLD
FPGA = Field Prog. Gate Array
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14. CPLDs and FPGAs
Complex Programmable Logic Device Field-Programmable Gate Array
Architecture PAL/22V10-like Gate array-like
More Combinational More Registers + RAM
Density Low-to-medium Medium-to-high
0.5-10K logic gates 1K to 500K system gates
Performance Predictable timing Application dependent
Up to 200 MHz today Up to 135MHz today
Interconnect “Crossbar” Incremental
Not shown: Simple PLD (SPLD) Architecture
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15. Programming Controller
XC CPLDs
Function
Block 1
JTAG
Controller
Block 2
I/O
Block 4 3
Global Tri-States
2 or 4
Block 3
In-System
Programming Controller
FastCONNECT
Switch Matrix
JTAG Port
Global Set/Reset
Global Clocks
Blocks 1
5 volt in-system programmable (ISP) CPLDs
5 ns pin-to-pin
36 to 288 macrocells (6400 gates)
Industry’s best pin-locking architecture
10,000 program/erase cycles
Complete IEEE JTAG capability
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16. XC4000 Architecture Programmable Interconnect I/O Blocks (IOBs)
Configurable
Logic Blocks (CLBs)
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17. Exponential Growth in Density
Year
Logic Cells
Logic Gates
1,000
10,000
100,000
1,000,000
1994
1996
1998
2000
2002
12M
1.2M
120K
12K
2 Million logic gates
Nov shipping world’s largest FPGA, XC40125XV (10,982 logic cells, 250K System Gates)
1 Logic cell = 4-input LUT + FF
175,000 Logic cells = 2.0 M logic gates in 2001 D Q FF
LUT
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18. XC4000E/X Configurable Logic BlocksD Q SD RD EC
S/R
Control 1 F' G' H'
DIN H
Func.
Gen. G F G4 G3 G2 G1 F4 F3 F2 F1 C4 C1 C2 C3 K YQ Y XQ X
H1 DIN S/R EC
2 Four-input function generators (Look Up Tables)
- 16x1 RAM or
Logic function
2 Registers
- Each can be
configured as Flip
Flop or Latch
- Independent
clock polarity
- Synchronous and
asynchronous
Set/Reset
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19. Look Up Tables
Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB
Example:
Look Up Table
Combinatorial Logic A B C D Z
4-bit address
A B C D Z
Capacity is limited by number of inputs, not complexity
Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM G
Func.
Gen. G4 G3 G2 G1 WE
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20. XC4000X I/O Block Diagram
Shaded areas are not included in XC4000E family.
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21. Xilinx FPGA Routing 1) Fast Direct Interconnect - CLB to CLB
2) General Purpose Interconnect - Uses switch matrix
3) Long Lines
Segmented across chip
Global clocks, lowest skew
2 Tri-states per CLB for busses
Other routing types in CPLDs and XC6200
CLB
Switch
Matrix
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22. Other FPGA Resources Tri-state buffers for busses (BUFT’s)
Global clock & high speed buffers (BUFG’s)
Wide Decoders (DECODEx)
Internal Oscillator (OSC4)
Global Reset to all Flip-Flops, Latches (STARTUP)
CLB special resources
Fast Carry logic built into CLBs
Synchronous Dual Port RAM
Boundary Scan
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23. What’s Really In that Chip?
CLB
(Red)
Switch
Matrix
Long Lines
(Purple)
Direct
Interconnect
(Green)
Routed Wires (Blue)
Programmable Interconnect Points, PIPs (White)
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24. Design Flow
XC4000 3
Design Entry in schematic, ABEL, VHDL, and/or Verilog. Vendors include Synopsys, Aldec (Xilinx Foundation), Mentor, Cadence, Viewlogic, and 35 others.
Implementation includes Placement & Routing and bitstream generation using Xilinx’s M1 Technology. Also, analyze timing, view layout, and more.
Download directly to the Xilinx
hardware device(s) with
unlimited reconfigurations* !! 1 2
*XC9500 has 10,000 write/erase cycles
M1 Technology
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25. Foundation Series Delivers Value & Ease of Use
Complete, ready-to-use software solution
Simple, easy-to-use design environment
Easy-to-learn schematic, state-diagram, ABEL, VHDL, & Verilog design
Synopsys
FPGA
Express
Integration*
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26. Xilinx Spartan/XL Series FPGAs
Similar to 4000’s, except ---
Synchronous RAM only
No RAM16X1, RAM32X1 (asynchronous)
Only RAM16(32)X1S, RAM16X1D
No Edge Decoders (wide AND of I/Os)
No DECODEx
BUFTs for Muxes only
No WANDx or WOR2AND
Serial configuration modes only
No master parallel or peripheral
Mode pins for configuration only
Not usable as I/O
No MD0, MD1, MD2
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27. Spartan/XL Family Benefits
Standard 5V and 3V supplies
3V Spartan-XL devices are 5V tolerant
Lowest power Xilinx FPGA family
Spartan-XL K factor is 11
Spartan-XL family adds power down pin
50 uA typical
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28. Spartan-XL Family Advanced 0.35m Process
Transistor gates 0.35
Allows 3.3 V supply
All other features 0.25
Small size
Low capacitance
Performance
Low power
Combines 3.3 V
operation with
0.25 benefits
Chip
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29. Spartan-XL Family Voltage Compatibility
Any
5 V
device 5V
Spartan-XL FPGA
Advanced 0.35
3.3V Core
3.3V I/O
3.3V
Meets TTL
Levels
Spartan-XL inputs accept 5V signals
Spartan-XL outputs drive standard TTL
100% compatible in 5 volt environment
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30. Spartan/XL Top-Level Architecture
Based on XC4000 Architecture
Logic is implemented in CLBs
IOBs provide the interface
between internal signals and
package pins
Routing channels provide paths
to interconnect the inputs and
outputs of CLBs and IOBs
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31. Spartan CLB Two 4-input LUTs and one 3-input LUT
Two edge-triggered FFs
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32. Spartan IOB
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33. Single-Port RAM Synchronous write, asynchronous read
16 x 2 or 32 x 1 max per CLB
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34. Dual-Port RAM One common synchronous write port
Two asynchronous read ports
16 x 1 max per CLB
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35. New Features in Spartan-XL Family
Higher speed (-4/-5)
8 flexible global low-skew buffers (BUFGLS)
CLB latches
Input Fast Capture Latch
Output multiplexer or lookup table
3.3V supply for low power with 5V tolerance
Programmable 3V input clamp for 3V PCI
Programmable 24 mA output drive for 5V PCI
Power-down pin
Improved boundary scan
Express parallel configuration mode
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36. Xilinx FPGA Family Summaries
Virtex Family
SRAM Based
Largest device has 1M gates
Configurable Logic Blocks (CLBs) have two 4-input LUTS, 2 DFFs
Four onboard Delay Locked Loops (DLLs) for clock synchronization
Dedicated RAM blocks (LUTs can also function as RAM).
Fast Carry Logic
XC4000 and Spartan Families
Previous version of Virtex
No DLLs, No dedicated RAM blocks
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37. Issues in FPGA Technologies
Complexity of Logic Element
How many inputs/outputs for the logic element?
Does the basic logic element contain a FF? What type?
Interconnect
How fast is it? Does it offer ‘high speed’ paths that cross the chip? How many of these?
Can I have on-chip tri-state busses?
How routable is the design? If 95% of the logic elements are used, can I route the design?
More routing means more routability, but less room for logic elements
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38. Issues in FPGA Technologies (cont)
Macro elements
Are there SRAM blocks? Is the SRAM dual ported?
Is there fast adder support (i.e. fast carry chains?)
Is there fast logic support (i.e. cascade chains)
What other types of macro blocks are available (fast decoders? register files? )
Clock support
How many global clocks can I have?
Are there any on-chip Phase Logic Loops (PLLs) or Delay Locked Loops (DLLs) for clock synchronization, clock multiplication?
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39. Issues in FPGA Technologies (cont)
What type of IO support do I have?
TTL, CMOS are a given
Support for mixed 5V, 3.3v IOs?
3.3 v internal, but 5V tolerant inputs?
Support for new low voltage signaling standards?
GTL+, GTL (Gunning Tranceiver Logic) - used on Pentium II
HSTL - High Speed Transceiver Logic
SSTL - Stub Series-Terminate Logic
USB - IO used for Universal Serial Bus (differential signaling)
AGP - IO used for Advanced Graphics Port
Maximum number of IO? Package types?
Ball Grid Array (BGA) for high density IO
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