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Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 CMS Tracker FED CMS Tracker System.

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Presentation on theme: "Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 CMS Tracker FED CMS Tracker System."— Presentation transcript:

1 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 CMS Tracker FED CMS Tracker System Meeting Test Rob Halsall et al 30 July 2001 CERN

2 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 3V CMS Tracker FED Test 96 ADC Module TTC FPGA Opto Rx PD Array Prog Delay 1 Synch & Processing TTCrx FE 1 9 SBC DAQ QDR SSRAM 1 SLINK VME BSCAN FPGA 3V2.5V1.8V Dual ADC 3V Dual ADC 1 6 3V FPGA Opto Rx PD Array 8 Synch & Processing FE 8 8 3V 2.5V 1.8V Dual ADC 3V Dual ADC 43 48 12 way FR Readout & Synch Control ASIC 3 Prog Delay 3 FPGA 12 FPGA FLASH VME Interface I2C 12 way FR BScan FPGA config 12 1 85 96 clk40 I2C 1 Temp Sense Temp Sense analoguedigital Clock inj TTS 3V

3 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 CMS Tracker FED System Overview Board Layout Reference adc TTCrx FE 1 DAQ TTC FE 2 FE 3 FE 4 FE 5 FE 6 FE 7 FE 8 360 MByte/s 150 MByte/s/% 100 KHz 360 MByte/s 96 ADC Channels VME FPGA SLINK PMC FE FPGA adc FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA RO FPGA SSRAMs Top view digital analogue VME Boundary Scan TTS

4 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 Test board CMS Tracker FED Test Post Assembly 1 adc TTCrx 96 ADC Channels VME FPGA Test board FE FPGA adc FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA RO FPGA SSRAMs Top view digital analogue PSU BSCAN CARD Loop back Analogue Scan I/O via Test Modules ‘Bed of Nails’ ATE test for Analogue? ‘Fying Probe’ test for Analogue? Boundary Scan Test digital devices Bounday Scan Test Modules for I/O Boundary Scan Test digital devices Bounday Scan Test Modules for I/O Opto Rx position Loop back Sysclock BSCAN Module Loop back Test board AFG or DAC BSCAN x12 x96 Assembly Company Simple Passive Loop back Version

5 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 FPGA Test Module CMS Tracker FED Test Post Assembly 1+ adc TTCrx 96 ADC Channels VME FPGA Test CMC FE FPGA adc FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA RO FPGA SSRAMs Top view digital analogue FPGA PSU BSCAN CARD or CHIPSCOPE Sysclock Bounday Scan Test Modules for connectors with digital signals CHIPSCOPE JTAG Readout… Boundary Scan digital devices ‘Bed of Nails’ ATE test for Analogue ‘Flying Probe’ ATE test for Analogue Boundary Scan digital devices ‘Bed of Nails’ ATE test for Analogue ‘Flying Probe’ ATE test for Analogue Test board Analogue signal Injection DAC/AFG Opto Rx position Assembly Company

6 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 Test board CMS Tracker FED Test Chipscope adc TTCrx 96 ADC Channels VME FPGA Test board FE FPGA adc FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA RO FPGA SSRAMs Top view digital analogue PSU Loop back Little design effort required Early readout of ADC data No VME Interface required Chipscope Logic Analyser per ADC embedded in FPGA Efffectively ‘Scope Mode’ with JTAG Readout Chipscope Logic Analyser per ADC embedded in FPGA Efffectively ‘Scope Mode’ with JTAG Readout Opto Rx position Loop back Test board AFG or DAC BSCAN x12 x96 Assembly Company Simple Passive Loop back Version Chipscope

7 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 FPGA Test Module PSU BSCAN CARD Sysclock CMS Tracker FED Test Post Assembly 2 adc TTCrx 96 ADC Channels VME FPGA FE FPGA adc FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA RO FPGA SSRAMs Top view digital analogue TTC Single DAC Opto Tx fanned out 96 way Boundary Scan controlled... Single DAC Opto Tx fanned out 96 way Boundary Scan controlled... Simple DC scan test of ADC bits Too complicated? BSCAN Controlled DAC & Opto Tx Assembly Company or RAL Test CMC FPGA

8 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 CMS Tracker FED Test Internal tests via VME adc TTCrx 96 ADC Channels VME FPGA SLINK CMC FE FPGA adc FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA RO FPGA SSRAMs Top view digital analogue VME VME SBC RAL EXT Clock Boundary Scan TTS CHIPSCOPE

9 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 CMS Tracker FED Test Performance/Soak adc TTCrx 96 ADC Channels VME FPGA SLINK CMC FE FPGA adc FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA RO FPGA SSRAMs Top view digital analogue VME BSCAN AFG & Opto Tx TTC System DAQ System VME SBC TTS Level of Analogue testing? crosstalk, performance... Level of Analogue testing? crosstalk, performance... CHIPSCOPE FPGA Embedded Logic Analysers readout via Boundary Scan CHIPSCOPE RAL

10 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 CMS Tracker FED Test In System adc TTCrx 96 ADC Channels VME FPGA SLINK PMC FE FPGA adc FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA RO FPGA SSRAMs Top view digital analogue VME Boundary Scan Detector TTC System DAQ System VME SBC TTS Detector Module Generate input test signals Detector Module Generate input test signals CHIPSCOPE FPGA Embedded Logic Analysers readout via Boundary Scan for commissioning CHIPSCOPE Detector RAL/CERN

11 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 CMS Tracker FED Test In System - other aspects adc TTCrx 96 ADC Channels VME FPGA SLINK PMC FE FPGA adc FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA BE FPGA SSRAMs Top view digital analogue VME Front End TTC System DAQ System VME SBC BE FPGA -> DAQ & TTS Generate input test signals to DAQ &TTS Fixed Pattern & Random Data Generation BE FPGA -> DAQ & TTS Generate input test signals to DAQ &TTS Fixed Pattern & Random Data Generation FED ‘SCOPE’ MODE + async Trigger Setup timing & calibration APV diagnostics Front End CERN Boundary Scan TTS CHIPSCOPE

12 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 CMS Tracker FED Test Equipment List JTAG Laptop & JTAG Software, USB-JTAG box, JTAG-I/O box, Cables & Connectors VME I/O Module, Analogue I/O Module, SLINK I/O Module Analogue Performance Tests Arbitrary Function Generator Analogue I/O Module Chipscope Kit Optical Test +Electrical-Optical Converter & Fanout Other Items TTC System, Clock Generator VME SBC, VME-PC Interface SLINK Modules Labview, VxWorks…. 9U VIPA Crate Cooled Rack, Cooler JTAG Laptop & JTAG Software, USB-JTAG box, JTAG-I/O box, Cables & Connectors VME I/O Module, Analogue I/O Module, SLINK I/O Module Analogue Performance Tests Arbitrary Function Generator Analogue I/O Module Chipscope Kit Optical Test +Electrical-Optical Converter & Fanout Other Items TTC System, Clock Generator VME SBC, VME-PC Interface SLINK Modules Labview, VxWorks…. 9U VIPA Crate Cooled Rack, Cooler

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