1. SR: 599 report Channel Estimation for W-CDMA on DSPs Sridhar Rajagopal ECE Dept., Rice University Elec 599

2. SR: 599 report Organization u W-CDMA. u DSPs in Wireless Communications. u Channel Estimation. u Aim of the 599 Project. u Implementation Issues and Results. u Future Architectures for Wireless systems. u Conclusions and Future Work.

3. SR: 599 report W-CDMA u Third Generation Communication Systems. u Multimedia Capabilities. u Multirate Services. u Quality Of Service. u Higher Data Rates. – 2Mbps, 384kbps, 144kbps.

4. SR: 599 report DSPs in Wireless Communications u Digital Signal Processor. u Signal ProcessingCommunications. u Features : – Low Power Consumption (1.2 V, 100 mW). – Low Cost (15$). – High Performance (100 MIPS).

5. SR: 599 report The Wireless Channel : Multiuser, Multipath Direct Path Reflected Paths Faces Attenuation, Delays and Doppler Effects : Unknown Channel Parameters Antenna

6. SR: 599 report At the Receiver DECODER DETECTOR DEMODULATOR R CHANNEL ESTIMATOR A, UZ

7. SR: 599 report ML Channel Estimation u Send a Preamble. u Channel properties embedded in received signal. u Compare and estimate. u Keep estimate for remaining data bits (static). u Repeat preamble every frame, if no tracking.

8. SR: 599 report Data Transmission in W-CDMA Mobile # 1. 2. 3. 4. 5. : time C1 C7C3 C2 C8 C4 C1 C2 Packet Preamble for Acquisition Packet for Data Transmission DS-CDMA with Slotted ALOHA

9. SR: 599 report W-CDMA- Implementation Issues u Computationally intensive algorithms. u Stringent Time, Power, Size constraints. u Pressure on existing hardware resources.  Real -time Requirements : 1ms10ms 0.25 ms Preamble Message Random Access Burst in Slotted ALOHA

10. SR: 599 report Aim of the 599 Project u Get a grasp of – W-CDMA. – DSPs. – Channel Estimation. u Implement ML Channel Estimation on DSPs. u Evaluate its performance (“Execution Time”). u Ways to improve the performance. u Future Architectures for Wireless Communications.

11. SR: 599 report COMMONCOMMON The ML Algorithm Complexity u Complex -Real Dot Product. u Complex-Real Matrix Product. u Complex -Real Product. u Real Square roots. – Solving quadratic equation for least squares fit. Assuming Unity Noise Covariance Offline

12. SR: 599 report TI TMS320C6701 EVM u 32-bit Floating Point DSP at 133MHz. – VLIW Architecture (8 IPC). – 8 Functional Units ( 2 Multipliers). – 32 registers in 2 files. – 64 Kb each Internal Program and Data Memory. u External Memory. – 256 Kb SBSRAM (Static RAM : faster). – 8 Mb SDRAM (Dynamic RAM : slower).

13. SR: 599 report Steps in DSP Implementation u Original Floating Point Code. u Remove File I/O. u Minimize use of functions. u Minimize use of temporary variables. u Pre-computed Data (Offline). u Use Specialized Approximate Instructions. u Use Assembly Code for critical part.

14. SR: 599 report Use of Approximate Instructions L = 150, P =3, N= 31, SNR = 5dB, SINR = -10 dB

15. SR: 599 report Use of Assembly Code L = 150, P =3, N= 31, SNR = 5dB, SINR = -10 dB

16. SR: 599 report Comparison with UltraSPARCII UltraSPARCII Super-scalar 4-way in-order 250 MHz VIS support L = 150, P =3, N= 31, SNR = 5dB, SINR = -10 dB

17. SR: 599 report Joint Estimation and Detection Improvement in performance as only subset of parameter extraction. Improvement in detector also?. L = 150, P =3, N= 31, SNR = 5dB, SINR = -10 dB

18. SR: 599 report Memory Issues Data sizes do not fit in Internal memory. Onus on Programmer. External Memory Latencies. Affects performance

19. SR: 599 report Improvements in Architecture u Internal Memory. – More internal memory required - On-chip DRAMs. u Data Prefetching. – Matrix oriented operations - Prefetch Buffers. u ASIC/FPGA Support. – Offload critical computations (Viterbi Decoder in C54) u Specialized Instructions. – Array Based instructions, Complex Arithmetic.

20. SR: 599 report Improvements in Compilers u Compiler Efficiency. – VLIW Compilers unable to extract all parallelism. – Assembly language subroutines. – Advantages of Architecture not used fully. u OS Support. – Memory Allocation by Programmer. – May not be optimal / Leads to Errors. – Compiler should assist. – Suggestions acknowledged by TI.

21. SR: 599 report Future Architectures for Wireless u Large On-chip Memory. u Low Cost / High Performance. u Low Power Consumption. u Multiple DSPs. u GPP-DSP-Coprocessor-ASIC-FPGA. u Vector IRAMs.

22. SR: 599 report Conclusions u Studied ML Channel Estimation on DSPs. u Effect of Approximations (1.1X). u Effect of Assembly (2X). u GPP Comparison (0.2227 X for 15 users). u Joint Estimation and Detection (2.92X for 15 users). u Memory issues: Does not fit in Internal Memory. u Real-time Requirements: Application Dependant.

23. SR: 599 report Future Work u Effects on Downlink. u Effects of A/D Converter. u Tracking, Multiple sensors, Doppler effects. u Subspace Based Channel Estimation. u Real-time Performance. u Architectures for Wireless Communications.