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CSV 889: Concurrent Software Verification Subodh Sharma Indian Institute of Technology Delhi Relaxed Memory Effects and its Verification
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Why Relaxed Memory Higher Performance How? – Speculative execution, buffering, caching, etc. This leads to nonintuitive execution Verification becomes difficult
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TSO – Total Store Order Exhibited in x86 h/w w-r relaxation (to different variables) All writes are totally ordered
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PSO – Total Store Order w-r relaxation + w-w relaxation too – to different variables All writes to the same variable are totally ordered
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Effects of RMM on Stateless Model Checking Explosion in the number of interleavings – Why? New bugs! T1() { int a; x = 1; a = y; print (“%d”, a); } T2() { y=1; b=x; print(“%d”, b); } TSO
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Effects of RMM on Stateless Model Checking Explosion in the number of interleavings – Why? New bugs! T1() { x = 1; y = 1; } T2() { if(y==1) if(x==0) ERROR(); } PSO Not reachable under TSO or SC!
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DPOR for TSO/PSO thread scheduling nondeterminism store buffering nondeterminism Key ideas – buffer bounding for aggressive optimization – shadow threads to model buffered writes
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Shadow Threads
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Must HB order between buffered writes and flushes to the memory BWs are omitted as they are thread local!
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Shadow Threads for PSO To model per-address store buffers in PSO – one shadow thread per var
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Advantages No need to distinguish edges from scheduling and buffering nondeterminism! Implies classical DPOR features are applicable!
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Changes in DPOR Defs Enabled/Done/BT set: sets of pairs of
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Changes in DPOR Defs Dependency Relation
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Buffer Bounding Flushing of writes can be delayed for finitely many subsequent writes
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Acknowledgements DPOR for RMM by Zhang, Kusano, Wang: PLDI 2015
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