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OPTIMIZING A MULTI- PROCESSOR SYSTEM Performing: Isaac Yarom Supervised by: Mony Orbach 15/5/2008 Annual Project – Semester A (2007-1) Mid-term presentation.

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Presentation on theme: "OPTIMIZING A MULTI- PROCESSOR SYSTEM Performing: Isaac Yarom Supervised by: Mony Orbach 15/5/2008 Annual Project – Semester A (2007-1) Mid-term presentation."— Presentation transcript:

1 OPTIMIZING A MULTI- PROCESSOR SYSTEM Performing: Isaac Yarom Supervised by: Mony Orbach 15/5/2008 Annual Project – Semester A (2007-1) Mid-term presentation

2 Introduction  A few teams from HS DSL are developing a multi-processors system that implements a recognition algorithm from REFAEL.  The system is design as SOPC using on multiple FPGA systems  Area on FPGA is an important constraint, there is a need to decide on system “configuration” that will supply the best performance on a given FPGA system.

3 Tools  Hardware:  PC system  GiDEL StartixII®  Development system:  Altera SoPC® + QuartusII  GiDEL ProcStar®  NiosII® based VPU  LBS developed  Host/Generator software

4 System overview

5 System overview (continued) Current state of system:  Nios VPU is implemented with C2H.  Some issues regarding size and speed  Switch system is implemented.  No support for asymmetric VPUs yet.  MultiFIFO communication between PC and FPGA has problems.  Implementation Generator team has contacted GiDEL in regards to this problem.

6 Project goals – Part A  Performance evaluation methods and tools  Define methods and tools to use  Implement needed tools  Define optimization constraints and trade offs  Software model  Design and Implement Performance simulator  Run on several configuration and produce recommendations for configuration to test on actual system.  Build Dummy-system (+ performance study)  Learn Tools: PROCWizard, SOPC  Learn System: Switch, Software application & VPU  Build dummy system and produce performance evaluation

7 Performance evaluation methods  Performance is evaluated in several levels:  VPU functions  VPU latency  System throughput  A “Software system” throughput will be measured as well to perceive FPGA system merit.

8 FPGA tools Ramp-up  Basic tutorials for PROCStar®  Basic NiosII® CPU on StarTIX card.  Integrating PROCStar, Quratus and SOPC Builder Basic design Basic VPU

9 Timeline – Part A

10 Presentation Notes  Profiling algorithm is first prority from performance tasks  Understand algorithm  Control C2H  If needed push other task to second semester


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