1. WP3 Meeting 8 th October 2015 Power Boards for TM stave status 30 boards received and tested – targeted for TM modules Testing communication with 1-wire controller Measuring efficiency and O/P voltage sweep range All 1-wire controllers work Provides enable/disable of FEAST2 converter and HV mux Output voltage sweep is in the range 1.35 to 3.4V Translates to a TM hybrid power range of approx. 0.5 to 3.25W Module power dissipation range of 1 to 6.5W Efficiency is in the range of 71.5% (1A load) to 72.5% (2A load) Further improvement can be obtained with a lower Vin (8V instead of 10V) Efficiency now at 74% (1A) and 75% (2A) Concern about “ground rise” in tape (resistive voltage drop) – will retain 10V Vin Full stave load, 1-wire communication not guaranteed with lower Vin for furthest modules 2 power boards are faulty – but hope to recover One suffered a head crash with the wire-bonder (damaged pot) Will use on an electrical module (pot not needed) Second has a ‘lifted’ trace on PCB Re-work should recover this CERN FEASTMP Module Vin=10V Power Board with Vin=8V 28 x Power Boards Vin =10V

2. Power Boards - next 26 will be shipped to RAL for TM stave Will go down next week (week beginning 12/10/2015) Two to be shipped to USA colleagues for evaluation Leaves 2 off for modules here in Liverpool Would like to investigate smaller coil value Removing 2 windings from existing coil to lower DC resistance Aim is to improve high load efficiency (by reducing I 2 R loss….) But at risk of increased o/p voltage ripple Meanwhile expecting another 80 bare PCBs from vendor – for electrical modules Have only 50 off FEAST2 converters in stock Plan is to order another 30+ Will go for component placement as soon as they’re received here in Liverpool But still need to address shield boxes – would like a mixed Al/Cu build Hopefully more on this soon

3. Populated Hybrid Panels – One step forward, 2 steps back… 2 panels recently went for SMD attachment at Norcott Technologies Used as a trial run to check SMD alignment was ok after reflow If all ok then go for bigger run of 10 panels Returned panels show SMD attachment is very good Visual inspection shows no problem with component alignment All circuits have released from the panel (after reflow) – no adhesion to panel (as encountered in the past) BUT Panels have come back showing localised delamination of Kapton layer from FR4 carrier Similar problem encountered by Birmingham last year when trying to ‘release’ circuits At the time thought this was due to incorrect temperature profile Temperature rate of change too great and thus incurring thermal shock resulting in delamination Panel’s are unusable due to tooling lands being affected – no longer planar w.r.t. hybrids Hybrids themselves are perfect, not being laminated to the panel – hope to recover them Flexible anchor tabs doing their job Example of completed circuits Panel showing areas of delamination

4. Populated Hybrid Panels – Possible scenarios Number of scenarios under investigation (as recommended by Norcott) Defective PCB Faulty bond-ply Mismatch in CTEs of layers Punishing temperature profile, though profile used is at the low end of the lead free profiles (see next slide) Moisture entrapment PCB manufacturer recommends bake out of circuits prior to SMD attachment and re-flow. This wasn’t done – needs to be requested Raises issue of panel storage Ideally need to be baked out and then bagged with desiccant (as a minimum) We haven’t been doing any of this… ???

5. Populated Hybrid Panels – Temperature Profiles Temperature profiles Ramp up 0.6°C/s Max Temp: 220°C Reflow time ~170s Ramp up 1.9°C/s Max Temp: 223°C Reflow time ~50s Ramp up 1.2°C/s Max Temp: 235°C Reflow time ~60s Norcott reflow temperature profile Birmingham reflow temperature profile Observations Liverpool reflow has lowest Max. temperature and Ramp up time BUT longest reflow time Birmingham and Norcott have similar reflow times and Ramp up times Birmingham Max. temperature close to Liverpool whilst Norcott is much higher But Birmingham and Norcott show delamination – Ramp up time?? Norcott reflow would appear to be at the low end of the spectrum for lead free process Can expect ramp up times of 3°C/s, Max temperatures of >250°C and reflow times up to 150s

6. 6 Populated Hybrid Panels – What next Investigate bake-out of circuits Polyimide (Kapton) is hygroscopic Bake-out normally recommended prior to reflow Reduces risk of delamination BUT can degrade solderability IPC-1601 specification for bake-out: Manufacturers suggest minimising both bake out time and temperature to minimise effect on solderability For ENIG, recommend 100 to 110°C for a max time of 3 hours Plan is to program re-flow oven in Liverpool to match temperature profile of Norcott Will then sacrifice a panel to check if delamination occurs If delamination occurs then propose bake-out of a separate panel Then repeat re-flow to see what happens

7. 7 Summary 30 Power Boards have been tested for efficiency and 1-wire functionality 28 are ok with the remaining 2 requiring some minor rework The 26 required for the TM stave program will be delivered to RAL next week Meanwhile another 80 off bare PCB Power Boards are due imminent Targeted for electrical modules First pass at SMD component stuffing has been semi-successful SMD attachment on hybrids looks very good BUT issue with localised kapton delamination from FR4 (after reflow) Suspect moisture entrapment – needs to be proven Program now being set up to prove this Hopefully will have an indicator whether this the problem (or not) very soon But does point to unsatisfactory storage of the circuits Which we will now have to address