1. CBP 2002ITY 270 Computer Architecture1 Module Structure Whirlwind Review – Fetch-Execute Simulation Instruction Set Architectures RISC vs x86 How to build a CPU Pipelining Performance and Memory Digital Logic, ALU Design, Data Representation Turing Machines, Embedded Architectures Input Output issues, Busses Performance Metrics, Trends in Architecture Future – Wetware, reconfigurable, array, …

2. CBP 2002ITY 270 Computer Architecture2 Work Up and Down!

3. CBP 2002ITY 270 Computer Architecture3 CPU Caches System Bus Memory I/O controllers bridges Disk, Mouse Displays Keyboards Ethernet I/O Buses Where we’re going x86 MIPS SPARC X-Box Game Cube Pico JAVA Wetware Reconfigurable Analogue Tiled CISC RISC Stack

4. CBP 2002ITY 270 Computer Architecture4 Let’s make a Calculator Keypad Lots of Electronics LCD Display Keypad LCD Display Code Memory Programmable Electronics A dedicated design...... or a re- usable design

5. CBP 2002ITY 270 Computer Architecture5 Stored Program Computer Memory Instruction Data Central Processing Unit How do we achieve programmability ? CPU Fetches program instructions and executes them – turns them into actions on data – into electronic signals. Program is just data which is interpreted by the CPU

6. CBP 2002ITY 270 Computer Architecture6 Von-Neumann Model Memory Input and Output Data Path (ALU, registers, buses) Control Logic Computer Engine divided into 5 components: Memory CPU Arithmetic Logic Unit (ALU) CPU Control Unit Input Output

7. CBP 2002ITY 270 Computer Architecture7 Von-Neumann Motherboard Input - Output Memory CPU IO Bus Slots http://www.sceptre.com

8. CBP 2002ITY 270 Computer Architecture8 What’s this about buses? Here’s two possible ways of connecting the components of a computer … Total network … not so goodBussed interconnect … OK

9. CBP 2002ITY 270 Computer Architecture9 So what’s a bus ? Connecting let’s say lights and switches needs a wire between each light-switch pair. That group of wires is a bus.. buffer Here both the disk and system unit need to send signals on the bus wires, but only one can do this at any time, otherwise BOOM! It’s the job of the buffer chips to select one device onto the bus at any one time. CE

10. CBP 2002ITY 270 Computer Architecture10 Types of Buses MEM CPU DISK IO MEM CPU DISK IO MEM CPU DISKIO Graphics IO MEM CPU DISK IO Steam Age Late 60’s 80’s Today Processor DependentProcessor Independent

11. CBP 2002ITY 270 Computer Architecture11 Addressing Memory 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 0 1 1 110110 (6) (3) There are 8 different comb- inations of 3 bits. So with 3 bits we can address 8 memory cells. With 6 bits we use 3 for a row select and 3 for a column select to address 8x8=64 memory cells.

12. CBP 2002ITY 270 Computer Architecture12 Address Calculations With 4 bits we can have 2 4 = 16 possible numbers. With 8 bits we can have 2 8 = 2 4 *2 4 = 16*16 = 256 numbers which range from 0 to 255. So a byte of data can represent numbers from 0 to 255. Ancient computers had a data bus made from 8 wires. Hence 8 bits. Hence numbers from 0 to 255. With 16 bits we can have 2 16 = 2 8 *2 8 = 256*256 = 65536 numbers which range from 0 to 65535. Steam age computers had 16-bit data buses so could address only 65536 bytes of data (64k) Steam Age Memory 16-bit address bus 8-bit data bus

13. CBP 2002ITY 270 Computer Architecture13 Pentium II Memory 00000000 00010008 001000016 001100024 010000032 010100040 011000048 011100056 This is a BYTE Memory bus is 64 bits (8 bytes) wide 64 bits 36 bits address 3 lowest bits always zero 36 bits

14. CBP 2002ITY 270 Computer Architecture14 Memory Structure Register Cell Memory Chip Cell Data Out Bus Data In Bus Address Bus

15. CBP 2002ITY 270 Computer Architecture15 Arithmetic-Logic Unit ALU ALU out in function 67 13 add Several functions offered : add sub and or mul div and 7,4 and 0111,0100 0111 and 0100 0100 Here’s what ‘and’ is

16. CBP 2002ITY 270 Computer Architecture16 Computer = ALU + Memory Registers ALU 3 2 5 2 3 Let’s try to compute 3 + 2 = 5 32 Go to jail and do not collect £200

17. CBP 2002ITY 270 Computer Architecture17 Registers ALU GPR Architecture (General Purpose Register) Let’s compute 3 + 2 = 5 again ! 32 5 3 2 2 3 5 5 Bus Y Bus X Bus W Put 3 on bus X Put 2 on bus Y Stuff X and Y into ALU ALU adds X and Y SLU send result to bus W Put bus W into Mem Our programmer needs to do this !

18. CBP 2002ITY 270 Computer Architecture18 GRP Machine Details Memory Registers r11 r0 r1 r2 r3 r4 r10 ALU.. 0 8 16 24 32.. Load from Memory Store to Memory Load reg from mem Add reg to reg into reg Store reg in mem Our programmer needs to do this !

19. CBP 2002ITY 270 Computer Architecture19 Accumulator Architecure Memory ALU.. 0 8 16 24 32.. Get 6 from Memory and ADD ! 6 7 7 1. Assume 7 is already in the accumulator. The programmer writes Accumulator 6 7 Add six 2. The ALU does 6 + 7 = 13 and writes the result back into the accumulator

20. CBP 2002ITY 270 Computer Architecture20 6. Onto the bus wires as signals 5. Memory stores these as bits 4. Instructions in memory are just numbers Program Memory 0 65 8 43 16 24 32 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 2. High Level Language 3. Assembler Instructions Load reg from mem add reg to reg into reg w = x + y 1. Application Let’s consider a spreadsheet cell which adds two numbers x + y. This cell and its instruction is in memory. But it is REPRESENTED in different ways

21. CBP 2002ITY 270 Computer Architecture21 Memory Hierarchy Bus Controller System Memory ALU r0 r1 r2 r3 CPU Chip Cache Memory In/Out Bus The closer to the CPU the faster the memory: REGISTER CACHE SYSTEM DISK Seriously Fast Fast Normal Speed Grind Disk

22. CBP 2002ITY 270 Computer Architecture22 … take a breather People see water as something to drink Fish see water as something to breathe What does water see water as?

23. CBP 2002ITY 270 Computer Architecture23 Let’s build a Computer Let’s take a RISC. What do we need ? Memory Registers ALU Control Circuits A programming language A good Name - Simple Although Meaningful

24. CBP 2002ITY 270 Computer Architecture24 What’s needed to build Sam-4 ? PC Code Memory Code Memory – to store the program Arithmetic – Logic Unit to do the maths business Registers to hold results of computations X Y W Y W r1 r2 r0 X Data Memory 0 1 7 mar mdr Data memory to hold source and results of our work

25. CBP 2002ITY 270 Computer Architecture25 Program Memory PC = 4 12 8 4 0 Code Memory add halt store load add Memory stores program instructions at a sequence of byte addresses. Each instru-ction is 32 bits, so the addresses increment by 4 bytes. Here the Program Counter input address 4 to the memory which reads out the data word (32 bits) at address 4. This is the inst- ruction ‘add’ Address in Data out

26. CBP 2002ITY 270 Computer Architecture26 Registers, Registers 1. Registers Store data at addresses. Yep, that’s Memory ! 3. Multiport Registers have an input port (W) where data is send to be written into the register file. 2. There are TWO read ports (X and Y) where data can be simultaneously read out of the reg file. 4. The addresses for the read ports (X and Y) and the write port (W) come in here. X Y W Y W r1 r2 r0 X

27. CBP 2002ITY 270 Computer Architecture27 Data Memory 0 1 7 mar mdr Here’s the memory The Memory Data Register (MDR) is a parking place for data coming and going from the memory. The Memory Address Register holds the address of the data location selected for read or write e,g, 7 7

28. CBP 2002ITY 270 Computer Architecture28 Here’s Sam Data Memory Instruction reg Code Memory ALU r1 r2 r0 X Y W XY W 0 1 7 mar mdr

29. CBP 2002ITY 270 Computer Architecture29 Sam 4 Simulator

30. CBP 2002ITY 270 Computer Architecture30 Fetch-Execute Cycle Fetch instruction from memory Decode the opcode Read any operands from data memory Execute instruction, store results (Very General description) ld r0, [1] 0100110100 … 1101 32 wiresGet contents of address 1 Put result into r0

31. CBP 2002ITY 270 Computer Architecture31 Fetch-Execute Cycle 1. Fetch instruction from memory 2. Decode the opcode and read any registers 3. Do any ALU operations 5. Write back results to registers (Much more Clever and Useful) add r3,r2,r1 Get contents of address 1 4. Do any Memory Access ALU <- r1 ALU <- r2 ALU add None needed r3 <- ALU

32. CBP 2002ITY 270 Computer Architecture32 First Example ld r0, [1] ld r1, [2] add r2,r1,r0 st r2, [7] Load r0 with data at address 1 Load r1 with data at address 2 Add r0 and r1. Put result in r2 Store r2 in memory address 7 Note each of these instructions runs through 5 steps of its own F-E Cycle

33. CBP 2002ITY 270 Computer Architecture33 1. Instruction Fetch Ld r0,[1] Code Memory Data Memory ALU r1 r2 r0 Ld 0 1 PC = 0 X Y W XY0 1 7 mar mdr

34. CBP 2002ITY 270 Computer Architecture34 2. Decode, Reg Ops Data Memory + Code Memory ALU r1 r2 r0 Ld r0,[1] Ld 0 1 PC = 4 1 X Y W XY0 1 7 mar mdr

35. CBP 2002ITY 270 Computer Architecture35 3. ALU Operation Code Memory Data Memory ALU r1 r2 r0 Ld r0,[1] Ld 0 1 PC = 4 1 1 1 X Y W XY0 1 7 mar mdr

36. CBP 2002ITY 270 Computer Architecture36 4. Memory Access Code Memory Data Memory ALU r1 r2 r0 Ld r0,[1] Ld 0 1 PC = 4 1 1 0 7 X Y W XY0 1 7 mar mdr

37. CBP 2002ITY 270 Computer Architecture37 5. Register Write Code Memory Data Memory ALU r1 r2 r0 Ld r0,[1] Ld 0 1 PC = 4 1 0 7 X Y W XY mar mdr

38. CBP 2002ITY 270 Computer Architecture38 1. Instruction Fetch Data Memory Code Memory ALU r1 r2 r0 X Y W XY W 0 1 7 add r2,r0,r1 add 2 0 1 PC = 4 mar mdr

39. CBP 2002ITY 270 Computer Architecture39 PC = 8 2. Decode, Reg Ops Y Data Memory + Code Memory ALU r1 r2 r0 X W XY W 0 1 7 add r2,r0,r1 add 2 0 1 mar mdr

40. CBP 2002ITY 270 Computer Architecture40 3. ALU Operation Data Memory Code Memory ALU r1 r2 r0 X Y W XY W 0 1 7 add r2,r0,r1 add 2 0 1 PC = 8 mar mdr

41. CBP 2002ITY 270 Computer Architecture41 4. Memory Access Data Memory Code Memory ALU r1 r2 r0 X Y W XY W 0 1 7 add r2,r0,r1 add 2 0 1 PC = 8 mar mdr

42. CBP 2002ITY 270 Computer Architecture42 5. Register Write W Data Memory Code Memory ALU r1 r2 r0 X Y W XY0 1 7 add r2,r0,r1 add 2 0 1 PC = 8 mar mdr