1. CS/CoE 536 : Lockwood 1 Step 1 : Submit Project Information Visit : http://www.arl.wustl.edu/~lockwood/class/cs536/project/index.html –Provide Project Title What do you plan to design and implement? –Identify Project Team Team Leader –Specialty –Email contact Team Member –Specialty.. Team Member –Specialty.. (2-4 people should be on a team)

2. CS/CoE 536 : Lockwood 2 Step 1 (cont) : Provide Project Information –Provide Project Description Provide 2-3 paragraphs of detail –What will it do ? –How will it do it ? –Where will it connect to the rest of the System on Chip ? –Identify Project Website Provide the URL to a homepage hosted by the project leader

3. CS/CoE 536 : Lockwood 3 Step 2 : Motivate the Problem –What is this problem interesting ? –How will this component improve the Internet ?

4. CS/CoE 536 : Lockwood 4 Step 3: Reference Related Work –What have others done ? References –How did the do it ? –Why is this problem hard

5. CS/CoE 536 : Lockwood 5 Step 4 : Describe your approach –How do you plan to solve this problem Theory Data structures Diagrams

6. CS/CoE 536 : Lockwood 6 Step 5: Specify Interfaces and Components Data Interfaces –Entity of new component External Memory Interfaces –Number of SRAM interfaces (0..2) –Number of SDRAM interfaces (0..3) Estimated Size –Number of LUTs –Number of BlockRAMs

7. CS/CoE 536 : Lockwood 7 Step 6: Provide a Block Diagram Show how your component will integrated into the System On Chip (SOC) –Show which interfaces your block will use –Show how your component interfaces to external SRAM or SDRAM memory (if applicable) –Examples give on the next page

8. CS/CoE 536 : Lockwood 8 p Block Diagram of SOC (Example 1) Layered Protocol Wrappers Content- based Match (regex) (MP2) Expanded CAM-based Firewall (MP1) Flow Buffer Queue Manager (MP 3) p p Match vector Flow# from CAM Head Pointers Tail Pointers SDRAM Free List Manager SDRAM Free pointers SRAM 1 Controller SDRAM 1 Controller Scheduler (RR, DRR, 3DQ) SDRAM 2 Controller Off-Chip SDRAM 1 Off-Chip SRAM 2 SRAM Controller Off-Chip SDRAM 2 Off-Chip SRAM 1 # SRAM (0..2)# SDRAM (0..3) My New Component p p = Available Interface = New Component = New Connectivity Show how your new component connects to the rest of the system on chip

9. CS/CoE 536 : Lockwood 9 p Block Diagram of SOC (Example 2) Layered Protocol Wrappers Content- based Match (regex) (MP2) Expanded CAM-based Firewall (MP1) Flow Buffer Queue Manager (MP 3) p p Match vector Flow# from CAM Head Pointers Tail Pointers SDRAM Free List Manager SDRAM Free pointers SRAM 1 Controller SDRAM 1 Controller Scheduler (RR, DRR, 3DQ) SDRAM 2 Controller Off-Chip SDRAM 1 Off-Chip SRAM 2 SRAM Controller Off-Chip SDRAM 2 Off-Chip SRAM 1 # SRAM (0..2) # SDRAM (0..3) My New Component p p = Available Interface = New Component = New Connectivity Show how your new component connects to the rest of the system on chip

10. CS/CoE 536 : Lockwood 10 p Block Diagram of SOC (Example 3) Layered Protocol Wrappers Content- based Match (regex) (MP2) Expanded CAM-based Firewall (MP1) Flow Buffer Queue Manager (MP 3) p Match vector Flow# from CAM Head Pointers Tail Pointers SDRAM Free List Manager SDRAM Free pointers SRAM 1 Controller SDRAM 1 Controller Scheduler (RR, DRR, 3DQ) SDRAM 2 Controller Off-Chip SDRAM 1 Off-Chip SRAM 2 SRAM Controller Off-Chip SDRAM 2 Off-Chip SRAM 1 # SRAM # SDRAM (0..3) My New Component p p = Available Interface = New Component = New Connectivity p

11. CS/CoE 536 : Lockwood 11 Implementation Plan Describe the Major Tasks –Describe the Minor Tasks