1. E NCRYPTION INFRASTRUCTURE ON - KEY Written by: Elkin Aleksey Savi Esacov Advisor: Mr. Idan Shmuel Winter 2013/14 Midterm Presentation

2. P ROJECT GOALS Creation universal infrastructure for encryption/decryption system using FPGA Creation GUI Creation control system for tracking data from PC to a SD card and back through encrypts / decrypts Learning and experience in a variety of areas : RealTime controlling system FPGA Programming

3. B ACKGROUND Now there are a lot of data encryption systems based on hardware These systems encryption mechanism and control system loose, so there is a dependence and lack of flexibility in the system Separation of encryption mechanism and the control system will increase the system flexibility, in particular allow to change the encryption mechanism according to the needs Now the lab are realizing the encryption and decryption mechanism, which is implanted into the shell we must build

4. I NSTRUMENTS Hardware DE2 Board NIOS II core DLP SD card Software Quartus II 13.0 Qsys Eclipse

5. P ROJECT G OALS Planning and creating an interface between the DE2 Board and SD card Planning and creating an interface between the DE2 Board and PC Planning and creating GUI Integration between parts of the system

6. DE2 Board FPGA SD Slot Number of files DLP Slot SD card present control Data size (in kilobytes) SD read/write controller DLP read/write controller

7. U SING THE NIOS TO CONTROL DATA TRANSMISSION NIOS II Data transmitter Data speed: 40 kbit per second

8. E XAMPLE – W RITE TO SD BY NIOS

9. E XAMPLE – D ATA ON SD AFTER WRITING

10. Soft NIOS II Core It’s the main controller of the system.

11. DLP-USB Interface between internal FIFO of FPGA and USB FIFO. Data speed: 1 MB per second.

12. SD CARD אמצעי אחסון מידע טורי. קצב כתיבה / קריאה מינימלי של 2 מ " ב לשניה. מערכת קבצים FAT.

13. A RCHITECTURE – H IGH L EVEL PC DLP SD card GUI Sending data to encrypt Or decryption request Nios II AVALON BUS controller EncryptionDecryption DataTransmitter (Option)

14. D ATAFLOW PCPC USB DLP SD card FPGA

15. A VALON B US Responsible for scheduling regimes between peripheral components connected to NIOS

16. ממשק בין FPGA ו DLP FIFO on chip memory 128-byte receive buffer 385 byte transmit buffer

17. P LANNING AHEAD Interface (synchronization) between software and hardware Limit number of logic elements

18. S CHEDULE TASK 20- Oct 27- Oct 03- Nov 10- Nov 17- Nov 24- Nov 01- Dec 08- Dec 15- Dec 22- Dec 29- Dec 05- Jan 12- Jan 19- Jan 23- Feb 02- Mar 09- Mar Getting Project Match expectations and study of NIOS Route data and knowledge its components Characterization Interface between SD and FPGA Interface to DLP Infrastructure for the encryption Planning and building of GUI Mid presentation Mid present. Integration Verification and Debugging Verification and Debugging Final presentation and report

19. T HE E ND