1. Parallel port FPGA X4X4 X3X3 X2X2 X1X1 7. Exercises for the laboratory work: Controlling of a seven-segment indicator. A four-order binary code is the output from the parallel port. The respective code must be shown in hexadecimal notation by firing necessary segments. 1. Laboratory work.

2. FPGA 12 MHz generator Example Compose a logical circuit that would fire in series 2 or 3 (the exact number is determined by the professor). Segments. Each pair or triplet has to burn 1-2 seconds. The “snake” consisting of the fired segments moves on the indicator according to the trajectory set by the professor. 2. Laboratory work

3. FPGA 12 MHz or 100MHz generator Side road - B Main road -A Parallelport X Compose the logic circuit, which drives the traffic lights on the road cross. On side road there is located a sensor, which is fixing the traffic situation there (is any car waiting?) If on the side road there are waiting cars, then it will be initiated after time period T 1 the procedure for lightning green on side road. The green light is on for side road during time period T 1 and there will be No additional sensor control if the main road will be under green condition. Times T 1 and T 2 will be given by the tutor. 3. Laboratory exercise.

4. Main road Side road X=1 Sensor check X=0 T1T1 T1T1 T2T2 T2T2 Main road Side road Sensor for cars waiting on side road Times T 1 and T 2 will be given by tutor.