1. Choice of Silicon Etch Processes for Opto- and Microelectronic Device Fabrication using Inductively Coupled Plasmas Colin Welch, Andrew Goodyear, Gary Ditmer and Glenn Tan Oxford Instruments Plasma Technology Different techniques to etch silicon １） Hydrogen bromide based Si and SOI etch process ２ ) Room temperature F-gas Si etch process ３） Cryogenic Si etch process Important features of a silicon etching process for micro- and nanotechnology １ ) Feature sizes down to 100nm or less with aspect ratios at least 2:1 ２ ) Controllable sidewall profile (generally vertical needed) ３ ) Smooth contamination free sidewalls ４） Sufficient selectivity over the mask and if applicable high selectivity over underlying layers ５） Good uniformity and good reproducibility Important features of ICP High ion density (>10 11 cm-3) Yet low process pressures Separate power for ICP and electrode -provides separate control over ion energy and ion density OIPT has optional cryo/hot electrode: -150°C to +400°C ICP gives excellent performance for Si etching, far exceeding RIE ProcessHBrRT F-baseCryogenic Depth [µm]0.05µm to 1µm0.05µm to 10µm0.2µm to >100µm Feature size [µm]>25nm Aspect ratio>5:1 >10:1 Etch rate [nm/min] >100>200>300 Uniformity< ± 5% Selectivity Si:oxide>100:1>10:1>30:1 Selectivity Si:resist>3:1>5:1>15:1 Profile 80-92 ̊ Sidewall roughness<5nm To exploit the excellent properties of silicon we often need to pattern by etching to fabricate devices *2-dimensional photonic crystals *Micro-silicon waveguides *Grating structures *Nano-SOI MOSFETs *Novel future opto- and microelectronic devices A. Hydrogen Bromide (HBr) based silicon-on-insulator (SOI) process 1) Selectivity control Oxygen substitution is used to raise selectivity of silicon over SiO 2. Fig. 3 shows that extremely high selectivities can be achieved once the O 2 level reaches about 10%. Figure 3: Selectivity of polysilicon over SiO2 as a function of O 2 flow Figure 4: HBr based etch of 90nm polysilicon lines and spaces stopping on 3nm gate SiO 2. HSQ masked. B. Room temperature fluorinated chemistry silicon etch process This option has the benefit of using a non-corrosive octofluorocyclobutane (C 4 F 8 ) – sulfur hexafluoride (SF 6 ) Figure 5: Vertical HBr-based SOI etch. Figure 6: Profile angle as a function of C 4 F 8 percentage in SF 6 Angles 90° a re-entrant profile Fig. 7 and Fig. 8 shows the flexibility of the process in its use for a 1µm wide x 5µm deep waveguide and for 50nm wide trenches (300nm deep) respectively. Figure 7: Room temperature F-based etch. 1µm wide x 5µm deep Si waveguide Figure 8: RT F-based etch. 50nm wide trenches in Si (6:1 aspect ratio). Courtesy of ITRI/MIRL, Taiwan C. Cryogenic silicon etch process The cryogenic silicon etching offers the best performance of all the options by using sub-minus 100ºC Figure 10: Cryogenic Si etch. 0.5µm wide waveguidesx10µm deep with no mask undercut (Courtesy of NCRC University of Tokyo) Figure 11: Cryogenic Si etch. 0.1µm gaps etched 1µm deep.Aspect ratio 10:1 Cryogenic Silicon Etch using SF6 / O2 F O FSi (Cryogenic temperature) O F F F O FO Etching (SiFx) Passivation effect (SiOxFy) Si Figure 1: ICP Process Chamber Figure 2: Si etch process comparison data Figure 9: Cryogenic Si etch mechanism