2. By Marek Perkowski Some slides of M. Thornton used Introduction

3. Introduction: What is the sense in MV logic

4. THE MULTIPLE-VALUED LOGIC. What is it? WHY WE BELIEVE IT HAS A BRIGHT FUTURE. Research topics (not circuit-design oriented) New research areas The need of unification

5. Is this whole a nonsense? “multi-valued logic is useless because nobody builds circuits with more than two values”When you ask an average engineer from industry, he will tell you “multi-valued logic is useless because nobody builds circuits with more than two values” FirstFirst, it is not true, there are such circuits built by top companies (Intel Flash Strata) Second minimize binarySecond, MV logic is used in some top EDA tools as mathematical technique to minimize binary logic (Synopsys, Cadence, Lattice) Thirdlyrealized in softwareThirdly, MV logic can be realized in software and as such is used in Machine Learning, Artificial Intelligence, Data Mining, and Robotics

6. multiple-valued logic Short Introduction: multiple-valued logic {0,1} - binary logic (a special case) {0,1,2} - a ternary logic {0,1,2,3} - a quaternary logic, etc Signals can have values from some set, for instance {0,1,2}, or {0,1,2,3} Minimal value MINMIN MAXMAX 21 Maximal value 1 2 1 2 3 23

7. Binary logic is doomed It dominates hardware since 1946 Many researchers and analysts believe that the binary logic is already doomed - because of Moore's Law indefinitelyYou cannot shrink sizes of transistors indefinitely aloneWe will be not able to use binary logic alone in the generation of computer products that will start to appear around 2020.

8. Quantum phenomena They will have to be considered in one way or another It is not sure if standard binary logic will be still a reasonable choice in new generation computing Biological models

9. Chip size and performance are increasingly related to number of wires, pins, etc., rather than to the devices themselves. Connections will occupy higher and higher percentage of future binary chips, hampering future progress around year 2020. In principle, MVL can provide a means of increasing data processing capability per unit chip area. MVL can create automatically efficient programs from dataMVL can create automatically efficient programs from data Future “Edge” of MVL

10. twomore From two values to more values The researchers in MV logic propose to abandon Boolean principles entirely multi-valuedfuzzycontinuousset quantum.They proceed bravely to another kind of logic, such as multi-valued, fuzzy, continuous, set or quantum. calculatingIt seems very probable, that this approach will be used in at least some future calculating products.

11. Synthesis Multi-Valued Logic Synthesis(cont) The MVL research investigates –Possible gates –Possible gates, connection structures –Regular gate connection structures (MVL PLA), –Representations –Representations - generalizations of cube calculus and binary decision diagrams (used in binary world to represent Boolean functions), –Application of design/minimization algorithms –General problem-solving approaches –General problem-solving approaches known from binary logic such as: generalizations of satisfiability, graph algorithms or spectral methods, application of simulated annealing, genetic algorithms and neural networks in the synthesis of multiple valued functions.

12. Binary versus MV Binary versus MV Logic Synthesis Research There is less research interest in MVL because such circuits are not yet widely used in industrial products MV logic synthesis is not much used in industry. Researchers in hundreds Only big companies, military, government. IBM The research is more theoretical and fundamental. You can become a pioneerYou can become a pioneer – it is like Quine and McCluskey algorithm in 1950 Breakthroughs are still possibleBreakthroughs are still possible and there are many open research problems Similarity to binary logic is helpful.

13. However………, MV gates exponential growthif some day MV gates were introduced to practical applications, the markets for them will be so large that it will stimulate exponential growth of research and development in MV logic. accumulated 50 years of researchand then, the accumulated 50 years of research in MV logic will prove to be very practical.

14. Applications Image Processing New transforms for encoding and compression Encoding and State Assignment Representation of discrete information New types of decision diagrams Generalized algebra Automatic Theorem Proving

15. History and Concepts

17. Jan Lukasiewicz (1878-1956) Polish minister of Education 1919 ternary predicate calculusDeveloped first ternary predicate calculus in 1920 multiple-valuedMany fundamental works on multiple-valued logic Emil Post,Followed by Emil Post, American logician born in Bialystok, Poland

18. Literals

19. Post Literals: 0 1 2 MV functions of single variable Generalized Post Literals: 0 1 2 1 1 2 2 1 2 1 11 2 2 2

20. Universal Literals: 0 1 2 210210 = wire 0 1 2 1 1 22 210210 = negation MV functions of single variable (cont)

21. Let us start with an example that will help to understand, MAXMIN Suppose that we have the following table, and we need to build a circuit with MV-Gates, (MAX & MIN). As we can see, this is ternary logic. Multiple-Valued Logic 00 2 2 2 01 - - 0,2 02 1,2 1,2 0,1 10 2 2 - 11 2 2 - 12 0 0 0 20 1 2 2 21 - 2 2 22 0 0 - a b c 0 1 2

22. 00 2 2 2 01 - - 0,2 02 1 1 0,1 10 2 2 - 11 2 2 - 12 0 0 0 20 1 2 2 21 - 2 2 22 0 0 - a b c 0 1 2 a 0,1 b 0,1 b 0,1 c 1,2 a 0,1 b 0,1 + b 0,1 c 1,2 “Covering 2’s in the map”

23. 00 - - - 01 - - - 02 1 1 1 10 - - - 11 - - - 12 0 0 0 20 1 - - 21 - - - 22 0 0 - ab c 0 1 2 a0a0 b 0,1 1.a 0,1 +1.b 0,1 “Covering 1’s in the map”

24. MVL Circuits MIN-gate MAX-gate

25. SOP = a 0,1 b 0,1 + b 0,1 c 1,2 + 1.a 0,1 +1.b 0,1 1 a 0,1 b 0,1 1 Min Max f c 1,2

26. Example of Application of logic with MV inputs and binary outputs to minimize area of custom PLA with decoders. Pair of binary variables corresponds to quaternary variable X a’+b’=X 012 a’+b=X 013 a b 0 1 0 10 1 2 3 a + b’ = X 023 a + b = X 123 (a + b’) *(a’+b)= X 023 * X 013 Thus equivalence can be realized by single column in PLA with input decoders instead of two columns in standard PLA

27. Multiple Valued Logic Currently Studied for Logic Circuits with More Than 2 Logic States –Intel Flash Memory – Multiple Floating Gate Charge Levels – 2,3 bits per Transistor http://www.ee.pdx.edu/~mperkows/ISMVL/flash.html Techniques for Manipulation Applied to Multi- output Functions –Characteristic Equation –Positional Cube Notation (PCN) Extensions

28. MVI Functions Each Input can have Value in Set {0, 1, 2,..., p i-1 } MVI Functions X is p -valued variable literal over X corresponds to subset of values of S  {0, 1,..., p-1} denoted by X S

29. MVL Literals Each Variable can have Value in Set {0, 1, 2,..., p i-1 } X is a p -valued variable MVL Literal is Denoted as X {j} Where j is the Logic Value Empty Literal: X {  } Full Literal has Values S={0, 1, 2, …, p-1} X {0,1,…,p-1} Equivalent to Don’t Care

30. MVL Example MVI Function with 2 Inputs X, Y –X is binary valued {0, 1} –Y is ternary valued {0, 1, 2} –n=2 p X =2 p Y =3 Function is TRUE if: –X=1 and Y= 0 or 1 –Y=2 –SOP form is: –F = X {1} Y {0,1} + X {0,1} Y {2} Literal X {0,1} is Full, So it is Don’t Care –implicant is X {1} Y {0,1} –minterm is X {1} Y {0} –prime implicants are X {1} and Y {2} 01 01 11 211 X Y F

31. MVL to encode binary logic

32. PLA with decoders abab cdcd X 012 Y 012 X 013 Y 013 X 023 Y 023 Y 123 X 123 decoders Standard PLA x x x x T1= (a’  b) (c  d) x x x T2 = (a’ + b’) (c’ + d) x Z=T1+T2

33. Such PLAs can have much smaller area thans to more powerful functions realized in columns The area of decoders on inputs is negligible for large PLAs Multi-valued logic is used to minimize mv- input, binary-output functions with capital letter inputs X,Y,Z,etc. PLA with decoders

34. Multi-output Binary Function Consider x y z f0f0 f1f1

35. Multi-output Binary Function Consider x y z f0f0 f1f1 x y z F W Characteristic Equation

37. Sum of Minterms

38. Positional Cube Notation (PCN) for MVL Functions Binary Variables, {0,1}, Represented by 2-bit Fields MV Variables, {0,1,…,p-1}, Represented by p -bit Fields BV Don’t Care is 11 MV Don’t Care is 111…1 MV Literal or Cube is Denoted by C(  )  00 010 101 *11

39. PCN for MVL Example Positional Cube Corresponding to X {1} is C(X {1} ) Since Y {0,1,2} is Don’t Care

40. PCN for MVI-BO Example View This as a SOP of MVI Function: F is the Characteristic Equation z abf 1 f 2 f 3 a ba b 10 100 a ba b 1001001 a b 0110001 a b01 110

41. List Oriented Manipulation Size of Literal = Cardinality of Logic Value Set x {0,2}  size = 2 Size of Implicant (Cube, Product Term) = Integer Product of Sizes of Literals in Cube Size of Binary Minterm = 1  Implicant of Unit Size EXAMPLE f (x 1,x 2,x 3,x 4,x 5,x 6 )

42. Logic Operations Consider Implicants as Sets –Apply ( , , , etc) Apply Bitwise Product, Sum, Complement to PCN Representation Bitwise Operations on Positional Cubes May Have Different Meaning than Corresponding Set Operations EXAMPLE Complement of Implicant  Complement of Positional Cube

43. MVL Logical Operations AND Operation – MIN - Set Intersection OR Operation – MAX - Set Union NOT Operation – Set Complement EXAMPLE

44. MVL Number of Functions of 1 Variable

45. Example of MV function minimization

46. Cube Merging Basic Operation – OR of Two Cubes MVL Operation – MAX is Union of Two Cubes EXAMPLE  = 1 {0,1} 0 1  = 0 {0,1} 0 1 Merge  and  into   = {0,1} {0,1}0 1

47. Multi-Output Minimization Example

48. Minimization Example (cont) Sum of Minterms (Fig. 10.7 PLA Implementation) Merging Merge 1 st and 2 nd Merge 3 rd and 4 th Merge 5 th and 6 th Merge 7 th and 8 th

49. Minimization Example (cont) Multi-Output Function Using of Multi-Output Prime Implicants (Fig. 10.8 PLA Implementation)

50. History again

51. Why we need Multiple-Valued logic? In new technologies the most delay and power occurs in the connections between gates. less gatesless number ofconnectionsless delayWhen designing a function using Multiple-Valued Logic, we need less gates, which implies less number of connections, then less delay. Same is true in case of software (program) realization of logic natural variablesAlso, most the natural variables like color, is multi-valued, so it is better to use multi-valued logic to realize it instead of coding it into binary.

52. MIN MAXIn multi-valued logic, the binary AND gate is replaced by MIN gate, and OR by MAX AND arithmeticmultiplicationmodulo multiplicationGalois multiplicationBut, AND can be also replaced by arithmetic multiplication, or modulo multiplication, or Galois multiplication modulo additionGalois addition Boolean Ring additionOR can be also replaced by modulo addition, or by Galois addition, or by Boolean Ring addition, or by…..

53. infiniteFinally, the number of values in infinite This way we get Lukasiewicz logic, fuzzy logic, possibilistic logic, and so on…This way we get Lukasiewicz logic, fuzzy logic, possibilistic logic, and so on… Continuous logics There are very many ways of creating gates in MVL They have different mathematical properties They have very different costs in various technologies The values and operators can describe time, moral values, energy, interestingness, utility, emotions …….

54. Mathematical, logical, system science, or psychological/ methodological/ philosophical foundations Functional completeness theory studies the construction of logical functions from a set of primitives and enumeration of bases. The problems which are investigated include: –classification –classification of functions –enumeration of bases –enumeration of bases of a closed subset of the set of all k-valued logical functions particular kinds of functions –study of particular kinds of functions (monotone, symmetric, predicate, etc.) in multi-valued logics.

55. Are we sure that Lukasiewicz was the first human who had these ideas? Buddhist logic,Some Chinese philosophers claim that the Buddhist logic, invented Before Christ Era, was very similar to fuzzy logic hundreds yearsRaymon Lullus (Ramon Llull) invented many concepts that were hundreds years ahead of his time

56. Raymon Lullus Raymon Lullus, 1235-1316 (probably)

57. “Cartesian Product”Creator of “Cartesian Product” binary counting systemCreator of binary counting system multi- valued logic and counting systemCreator of multi- valued logic and counting system logic computerCreator of the concept of logic computer

58. Lotfi Zadeh (1921- ) Father of Fuzzy Logic Professor of University of California in Berkeley First paper on fuzzy logic published in 1956

59. Continuous Logic

60. From two values to many values to infinite number of values –Fuzzy logic (Lotfi Zadeh), –Lukasiewicz logic, –Probabilistic logic, –Possibilistic logic, –Arithmetic logic, –Complex and Quaternion logic, –other continuous logics software Find now applications in software and in hardware Are studied now outside the area of MV logic, but historically belong to it.

61. Example:Arithmetic Logic A  B = A+B - A*B Logic sum Arithmetic sum We express logic operators by arithmetic operators A=0.5 B=0.5 then result = 0.5+0.5- 0.5*0.5=1-0.25=0.75 1-(1-A)(1-B)=1-(1-A-B+AB)=A+B-AB This corresponds to probabilistic reasoning

62. Example:Arithmetic Logic A  B = A+B - 2*A*B Logic exor Arithmetic sum We express logic operators by arithmetic operators A=0.5 B=0.5 then result = 0.5+0.5- 2*0.5*0.5=1-0.5=0.5 A  B = A’B + AB’=(1-A)B+A(1-B)-(1-A)B(1-B)A=B-AB+A- AB-AB(1-A)(1-B)=A+B-2AB-AB(1-A-B+AB) In this definition, the same results for natural numbers 0 and 1, but slightly different for A=B=0.5 Various operators can be defined to model certain reasonings and because their hardware realization is simple Check it, define other operators of similar properties.

63. Functional Representations in Logic Synthesis compact representationNew representations aim at more compact representation of discrete data that allows: – less memory space, – smaller processing time. Data can be functions, relations, sets of functions and sets of relations. Result of logic synthesis is a computer program for a robot Logic Synthesis = Automatic Program Synthesis Good synthesis = better program (smaller, faster, more reliable - noise, generalization)

64. Examples of representations : Cube Representation 1. Cube Representation and the corresponding Cube operations (Cube Calculus). Decision Diagram 2. Decision Diagram (DD) Representation and the corresponding DD operations. Labeled Rough Partitions 3. Labeled Rough Partitions encoded with BDDs.

65. Cube Representations : 1-a. Graphical Cube Representations of Multi-Valued Input Binary Output. a b c d 00 01 02 10 11 12 20 21 22 00 01 02 10 11 12 20 21 22 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Cube

66. 1-b. Expression (Flattened Form) Representation of Cubes of Multi- Valued Input Binary Output. For the previous example :- F = 1.a 0 b 0 c 0 d 0 + 1.a 0 b 0 c 0 d 1 + 1.a 0 b 0 c 1 d 0 + 1.a 0 b 0 c 1 d 1 + 1.a 1 b 0 c 0 d 0 + 1.a 1 b 0 c 0 d 1 + 1.a 1 b 0 c 1 d 0 + 1.a 1 b 0 c 1 d 1 = 1. a 0,1 b 0 c 0,1 d 0,1

67. Tabular Representation Cube# a b f g 0 0,2 1 _ 2 1 0,1 0 0,2 0 2 2 0 1,2 0 3 1 1 1,2 2 mappings Functions and Relations are just mappings

68. To recognize faces we obtain the following tabular representation :- N H M S Person John 1 1 1 1,2 Peter 2 0 1 0,1 Philip 0 1 0 1,2 Ken 2 0 2 2 Cubes Input Features Output is a relation due to the imprecise measurements of S

69. f a 0 1 2 Multi-valued Logic Expand the function with respect to variable ‘a’ first. Step 1: Expand the function with respect to variable “a”,”b” and “c”. To get it’s Decision Diagrams, we follow these steps. 00 0,1 1 1,2 01 1 0,1 2 02 1 0,1 2 10 0 - - 11 0 2 0 12 1,2 1,2 0,2 20 - - 0 21 2 2 2 22 0 2 0 a b c 0 1 2

70. When a=0, expand the function with respect to ‘b’ and ‘c’. b=012 Multi-valued Logic 1 f equals ‘1’ here no matter if c is 0, 1 or 2, so it terminals at 1. Because this group can be 1, the 0 can be ignored 0 1 2 120,1 0 1 2 12

71. a=1 b= 012 Multi-valued Logic 02 02 002 1

72. a=2 b=012 Multi-valued Logic 0 2 0 2 02 1 0

73. a f bbb cc 0 1 2 0 1 2 1 02 121 1 02 121 1 c 0 1 2 02 02 002 1 c 012 02 Step 2: Draw the Decision Tree 02 002 1 Choice done for simplification

74. Multi-valued Logic a f bbb c 0 1 2 0 1,2 1 2 0,1 c 0 1 2 0,2 1 0 1 2 Step 3: Combine the same terminals to get Decision Diagram 201

75. FUTURE RESEARCH AREAS AND ANALOGIES

76. First Extension from Binary Binary Logic ------------ MV Logic And Gate ----------------------- MIN gate Or Gate -------------------------- MAX gate Inverter -------------------------- Literal Post, generalized Post or Universal complete This is standard, many published results, both two-level and multi-level, complete system

77. Second Extension from Binary Binary Logic ------------ MV Logic And Gate <---------------------  Galois Multiplication gate EXOR Gate <--------------------  Galois Addition gate Inverter <------------------------  Power of variable This system was introduced by Pradhan and Hurst, few papers have been published, no software, most is two-level logic

78. Another very recent extension Binary Logic ------------ MV Logic And Gate  -------------------  MIN gate Exor Gate  -----------------------  MODSUM gate Inverter  -----------------------  Literals This system was introduced by Muzio and Dueck and independently by Elena Dubrova in her Ph.D. Two papers have been published. Recent interest. Perhaps universal literals will increase the power, not investigated yet

79. Problems to think about 1.What is multivalued logic. 2.Can multi-valued logic be used to synthesize binary circuits? 3.Ternary logic, prime implicants and covering. 4.Continuous and Arithmetic logic 5.Multi-valued decision trees and diagrams. 6.Types of MV literals. 7.Types of MV logic. 8.PLA with decoders and how it relates to MV logic.