1. 2/5/06G. Stefanini/P326 SPC Ref/GTK WG1 Progress on Gigatracker Pixels Sensors Bump bonding Pixel ASIC and readout electronics Detector configuration Cooling Simulations Based on GTK Working Group meeting of 3 April 06 and latest updates

2. 2/5/06P. Riedler2 IRST-itc Sensor Wafer T B C. Piemonte, A. Pozza, M. Boscardin

3. 2/5/06P. Riedler3 Diodes - Pre-Irradiation Tests I-V and C-V measured in RD50 lab at CERN Total leakage current at 23.7°C C-V indicate V fd ~15V One diode (B1) with higher current (~4µA)

4. 2/5/06P. Riedler4 Diodes Irradiation in Ljubljana TRIGA reactor, 250kW, irradiation with fast neutrons All diodes biased at 30V during irradiation Guard and pad contact connected together Fluence levels from 1.0x10 12 to 2.0x10 14 ( 1 MeV n eq/cm 2 ) - including 2x safety factor Immediately after irradiation stored in freezer (-20°C) A1,B1 A2 B4 B3 B2

5. 2/5/06P. Riedler5 Study of Radiation Damage in Diodes Annealing measurements (CERN + Ferrara) –According to ROSE standards with I-V and C-V –Measurements last week on 5 irradiated diodes at 80 degC –Bias voltage up to 400V in order to verify the current stability –One diode also measured after full annealing with bias up to 1,000V ===> no indication of breakdown –The current behaviour at low bias voltage needs further study Measurements just completed, analysis under way Further work –More irradiations at the T7 facility at CERN

6. 3/4/06P. Riedler6 Sensor Wafers Processing Two sensor wafers sent to VTT for processing (end 2005) Visual inspection showed excellent quality Both wafers showed strong bow (~60-70µm) –potential problem for bump bonding process (requires < 30µm) Both wafers broke up in the photo-resist track at VTT –probably due to the bow of the wafers combined with tight dimensional tolerances in the automated centering stage The limit settings have been changed More wafers reworked by IRST ==> smaller bow

7. 3/4/06P. Riedler7 A. Pozza

8. 3/4/06P. Riedler8 A. Pozza

9. 2/5/06G. Stefanini/P326 SPC Ref/GTK WG9 Wafer Processing and Bump Bonding at VTT (II) In week 9: fire incident in one of the VTT clean rooms Electroplating benches (Ni and Pb-Sn deposition), reflow oven (bump bonding) and CMP machine (thinning) were affected Equipment cleaned, inspected and moved to second clean room First ladders delivered this week

10. 2/5/06G. Stefanini/P326 SPC Ref/GTK WG10 Readout wafers (200mm diameter) target thickness: 100µm or less, to reduce material budget –sensor wafers thickness is constrained by signal amplitude One blank wafer thinned successfully to 100µm Upcoming tests: thin (dummy) bumped wafer to 100µm Discussion with VTT end of March on thinning - several points of concern (e.g. stress effects) discussed and tests planned Thinning at VTT (I)

11. 2/5/0611 1st GTK chip design meeting Where, when, who Torino, 21.03.2006 People attending the meeting: –Ferrara: A. Cotta Ramusino, R. Malaguti –Torino: A. Rivetti, G. Mazza, S. Martoiu, A. La Rosa –CERN: A. Kluge, S. Tiuraniemi, G. Anelli G. Anelli

12. 2/5/0612 First important decision taken We made the choice of using a 0.13 um CMOS technology. The main reasons behind the choice are: –The 0.25 um technology might not be available to us at the time of production of the chip; –The design kit of the 0.25 um technology is not maintained anymore; –The 0.13 um technology will be available to us for many years in the future; –The 0.13 um technology offers a superior performance for digital circuits; –Most of the problems of using this technology are solved or being solved: more and more people in the community are using it, a design kit is going to be prepared soon, CERN will have a frame contract with a vendor and will organize frequent MPWs as it has been done for the 0.25 um technology in the past. G. Anelli

13. 2/5/0613 Second important decision We plan to submit a test chip containing several test structures and basic blocks in August – October 2006. An exact date has not been fixed yet, this depends also on the outcome of CERN’s call for tender. One option could be to submit a 10 mm^2 chip on the 7th of August through Mosis (IBM 0.13 um LM technology). We decided to share the responsibilities as follows: –Preamplifier:Giovanni A., Angelo R., maybe Sakari T.; –Current mode CFD:Sorin M.; –One TDC per pixel:Angelo R., Sorin M.; –Time over threshold:Alex K., Giovanni A.; –CFD:Angelo C.R., Roberto M., Stefano C.; –General architecture, trigger:Alex K., Gianni M.; –T.D.C.:Gianni M., Sakari T.; –Substrate noise:Sakari T., Giovanni A.; –LVDS buffers:Sakari T.; –RC delay and jitter in lines:Angelo C.R., Roberto M., Stefano C. G. Anelli

14. 2/5/0614 Issues still under discussion Time-walk cancellation is a very critical issue to get the necessary timing resolution. This is also why we will investigate in parallel several possibilities (2 CFD architectures and TOT); In the first test chip we might not be using enclosed transistors, if this gives problem with the extraction. Nevertheless, all the designs have to be made keeping in mind the limitations of using ELTs; LVDS drivers: what is the C of what we are going to drive with them? Question about DC or AC coupling; Having two power supplies implies more lines and more material budget; How will we test the blocks. We stress the importance of thinking about how to test what we design when we design it. Also, whenever it is possible, we should include testability features; How to cover the beam area is a hot topic. The solution with a 21 mm long chip biased on one side only seems not feasible. Power drops on the power distribution lines will be important. Also, we all agree that 3 mm are not enough to fit all the circuitry we need outside the matrix. G. Anelli

15. 2/5/06A. Kluge15 General: Chip Specifications Chip Parameter SpecificationPreliminary Design parameter Time resolution 160/200 ps160/200 ps (bin size?) Beam size (a x b) 48 x 36 mm 2 Pixel size (a x b) 300 x 300 µm 2 Matrix size (a x b) 32 x ? Active area/per chip (a x b) 9.6 x ? mm 2 # chip/module (a x b) 5 x 2 / 5 x 3 / 4 x 3 Calculation,simulationWorking parameters

16. 2/5/06A. Kluge16 General: Chip Specifications Chip Parameter First ideasSpecificationPreliminary Design parameter Avg Rate: avg/max 60/173 MHz/cm 2 Depends on TDC, segmentation Efficiency99% 98% for center?? Number of pixels/segment 1 (analog TDC) 7-20 (digital TDC) Dead time of segment 100 ns for 1 TDC/pixel 7 -10 ns for shared TDC Buffer size per segment Readout speed/Trans- mission speed Needs to operate in vacuum Yes/no ??

17. 2/5/06A. Kluge17 Configuration

18. 2/5/06A. Kluge18 Chip size Readout and supply 21 mm18 mm 3 mm Readout needs possibly more space -> not leaving 18mm active area Supply from one side has strong power drop Thinning of long narrow chips more difficult Readout and supply

19. 2/5/06A. Kluge19 Configuration Highest rate

20. 2/5/06A. Kluge20 Configuration Max rate on one chip, but chip smaller

21. 2/5/06A. Kluge21 Configuration 3 x 4 Assume matrix of 40 rows x 40 columns: –12 mm x 12 mm = 144 mm 2 Chip size –(12 + (2 x 3mm)) x 12 mm = 18 x 12 mm Pixel size 300 um x 300 um –=> 40 x 40 pixels = 1600 pixels Max. Avg Rate of center chip: ~150 MHz/cm 2 (for beam with max. 173 MHZ/cm 2 ) –=> 135 kHz/pixel –=> 216 MHz/chip –=> 216 MHz/chip * ~32 bit = 6.9 Gbit/s

22. 3/4/0622

23. 3/4/0623

24. 2/5/06G. Stefanini/P326 SPC Ref/GTK WG24 Material Budget - Cooling Conflicting requirements on detector configuration Material budget –crucial issue - should be minimized (simulations) –2x4 (or 2x5) detector configuration preferred –long chips with power/readout pads on one short side only Chip design –3x4 (3x5) detector configuration preferred –shorter chips with power/readout pads on both short sides Cooling –same considerations as for material budget –average temperature and thermal gradients should be minimized

25. 2/5/06G. Stefanini/P326 SPC Ref/GTK WG25 Preliminary Cooling Model & Estimates (I)

26. 2/5/06G. Stefanini/P326 SPC Ref/GTK WG26 Preliminary Cooling Model & Estimates (II)

27. 2/5/06G. Stefanini/P326 SPC Ref/GTK WG27 Summary Progress in all areas –Sensors: prototyping, radiation testing, bump bonding –Chip design: decision taken on choice of technology, defined sharing of tasks, MPW submission in preparation –Detector configuration and cooling: evaluation of options –Simulation Further progress critically depends on deeper understanding of material budget constraints ( ==> fast simulation, full GEANT simulation) Concerns on resources –Manpower: urgently need 2 (3) students at CERN (staff currently fully booked for LHC experiment) –Funding: cost of materials, wafer processing, bump bonding, MPW submission