1. Clocking System Design
Synchronous System Design
Current state determines the next state
Requires clock
1) FSM (Finite State Machine)
inputs
outputs
C/L
current
state bits
Next
state bits
CLK
Next state as a function of current state
& external inputs

2. Inputs should be stable before latching!
2) Pipelined system
inputs
C/L
C/L
outputs
CLK
No feedback
(feedback thru MUX)
Inputs should be stable before latching!

3. Register overhead > latch overhead (tsetup + tclk-q) (td-q)
Clocking Overhead
Latch
Register (or F/F) D D   Q Q
td-q
tsetup
tclk-q
Register overhead > latch overhead
(tsetup + tclk-q) (td-q)

4. Clock skew tdmax tdmin comes from 1) gated or buffered
2) RC delay with clock wire
cycle time gets longer by tskew
tcycle=td+tskew
-> No setup time violation
Malfunction : hold time violation
if tskew > tsetup+ tclk-q
tdmax R E G R E G
Logic
Late
Early
tdmin R E G R E G
Early
Late

5. No Clock (Wave Pipelining)
- match the logic delay
C/L
C/L
C/L
C/L
C/L
- Multiple outputs of logic blocks
come out at the same speed
- Constraint
at all possible path
- used in some memory design

6. Pulse Mode Clocking tw tc
- All loops of logic broken by a single latch
- Clock w/narrow pulse L A T C H L A T C H
C/L
CLK
CLK
Clock pulse should be
shorter than the slowest
path of the logic
CLK tw tc
- Timing Requirements
-Used in original Cray Computer (ECL machine)

7. Pulse Mode Clocking (cont’d)
- Advantages: 1) small clocking overhead
(one latch delay per clock)
2) high performance
- Disadvantages:
1) Double-sided timing constraints
If logic is too slow or too fast, the system will fail
2)Pulse width critical
 hard to maintain narrow pulse thru inverter chain
3) Not recommended for novice designer

8. Single-Phase Edge Triggered Clocking
- Use Registers instead of latches
- Popular in ASIC design (Gate arrays & Std Cells) R E G R E G
C/L
- Timing Contraints
- Problem: Delayed clock skew (latch closes after data change)
 Can’t change the clock
Can’t make the circuit work
SLOW operation of CLK will not fix this problem
Need to redo the chip
(Early clock)-> setup time violation
(Late clock) -> hold time violation

9. Avoid clock skew problem
Data Flow R E G R E G
delay
Clock propagation
1) No hold time violation
2) Tc= Tq + Td + Tsetup + Tskew
Td < Tc - (Tq + Tsetup + Tskew)
smaller margin for logic design
Tskew < 0   clock skew constraint is unconditionally met
 guaranteed operation (No hold time violation)
clk-to-q logic delay clk skew

10. Two-Phase Clocking
- Use different edges for latching the data & changing the output
C/L

11. Effectively 1
comes before 2
by t12 .
 Can make circuit work by
increasing t12 & reducing
clock frequency
Tc increased by t12