1. Electronic System Design GroupInstrumentation DepartmentRob HalsallRutherford Appleton Laboratory19 July 2002 Electronic System Design Group CMS Tracker FED Update 25th July 2002 09:00 - 12:00

2. Electronic System Design GroupInstrumentation DepartmentRob HalsallRutherford Appleton Laboratory19 July 2002 0V CMS Tracker FED Functionality TTC Front End FPGA 12x Opto Rx PD Array 4x Prog Delay 1 Synch & Processing TTCrx FE 1 9 VME QDR SSRAM 2 5V3.3V1.5V Dual ADC 3.3V Dual ADC 1 6 0V Front End FPGA 12x Opto Rx PD Array Synch & Processing FE 8 8 Dual ADC Dual ADC 85 48 12 way FR Readout & Synch Control ASIC FPGA 12 way FR 12 1 1 Temp Sense Temp Sense 4x Prog Delay FPGA 1 4 4x Prog Delay FPGA 4x Prog Delay FPGA 1 4 Temp Sense Temp Sense 3.3V 1.5V 5V -5V spare PD Boundary Scan System ACE Hot swap PSU & DC-DC Back End FPGA Temp Sense 12x trim dac Buffer Switch Matrix Compact Flash VME64x Interface FPGA Test Connector SW Hot swap cycle Live extract request E2 PROM Vref DAQ TTS Spare 1.5V 3.3 V 5.0 V 2.5V -5.0V 2.5V 12 1 Vref

3. Electronic System Design GroupInstrumentation DepartmentRob HalsallRutherford Appleton Laboratory19 July 2002 Front End Module Layout 9U Envelope - Active Components Opto Rx NGK 45 mm Double Sided Single Sided 130 mm 27 x 27 mm 12 x 12mm 9 x 9 mm 5 x 3 mm 33 x 40 mm FPGA XC2V1000- XC2V3000 FG676 FPGA XC2V40 CS144 ADC AD9218 ST48 DIFF OP-AMP AD9218 RM8 N.B. No Passives Shown

4. Electronic System Design GroupInstrumentation DepartmentRob HalsallRutherford Appleton Laboratory19 July 2002 CMS Tracker FED Board Layout Overview RO FPGA VME FPGA FED Channel Link 800MByte/s DAQ TTS

5. Electronic System Design GroupInstrumentation DepartmentRob HalsallRutherford Appleton Laboratory19 July 2002 CMS Tracker FED System Overview Back End Layout Preliminary mR FET 3V3 FET 5V0 FET 12V0 VME J1 VME J2 V M E J0 22501 244 5906 DC-DC 1.5V / 20A SVP VME FPGA BE FPGA Pin DiodeQDR TTC rx QDR 40240 4043 FUSE 70734002 7073 ISOLATED +5V IN ON+5V IN SYS ACE COMPACT FLASH XC18V04 X24165 DC-DC -5V / 4A mR FET 1V5 NB Single sided only shown

6. Electronic System Design GroupInstrumentation DepartmentRob HalsallRutherford Appleton Laboratory19 July 2002 CMS Tracker FED System Overview Board Layout FED mR FET 3V3 FET 1V5 FET 5V0 FET 12V0 VME J1 VME J2 V M E J0 22501 244 5906 DC-DC 1.5V / 20A SVP VME FPGA BE FPGA Pin DiodeQDR TTC rx QDR 40240 4043 FUSE 70734002 7073 ISOLATED +5V IN ON+5V IN SYS ACE COMPACT FLASH XC18V04 X24165 DC-DC -5V / 4A