2. Fall 2004ICOM 4036 Programming Laguages Lecture 2 1 Low-Level Programming Prof. Bienvenido Velez ICOM 4036 Lecture 2

3. Fall 2004ICOM 4036 Programming Laguages Lecture 2 2 Part I The Nature of Computing Part II Practical Computing Devices

4. Fall 2004ICOM 4036 Programming Laguages Lecture 2 3 Some Inaccurate Yet Popular Perceptions of Computing Computing = Computers Computing = Programming Computing = Software

5. Fall 2004ICOM 4036 Programming Laguages Lecture 2 4 Computing = Computers Computing is about solving problems using computers A.K.A. The Computing Device View of Computing

6. Fall 2004ICOM 4036 Programming Laguages Lecture 2 5 Computing = Programming Computing is about writing programs for computers A.K.A. The Programming Language view of Computing

7. Fall 2004ICOM 4036 Programming Laguages Lecture 2 6 Computing = Software Computing is not concerned with hardware design A.K.A. The “Floppy Disk” view of Computing

8. Fall 2004ICOM 4036 Programming Laguages Lecture 2 7 Part I - Outline What is Computing? Computing Models and Computability Interpretation and Universal Computers Church’s Thesis

9. Fall 2004ICOM 4036 Programming Laguages Lecture 2 8 What is computing then? Algorithmic Computation Function Input Information Output Information Computing is the study of Computation: the process of transforming information

10. Fall 2004ICOM 4036 Programming Laguages Lecture 2 9 The Computation Process 01101100 1010100 101… encode 01101100 1010100 101… compute Problem decode Solution Information

11. Fall 2004ICOM 4036 Programming Laguages Lecture 2 10 Fundamental Questions Addressed by the Discipline of Computing What is the nature of computation? What can be computed? What can be computed efficiently? How can we build computing devices?

12. Fall 2004ICOM 4036 Programming Laguages Lecture 2 11 The Computation Process 01101100 1010100 101… encode 01101100 1010100 101… compute Problem decode Solution Integer Function

13. Fall 2004ICOM 4036 Programming Laguages Lecture 2 12 Computability All Integer Functions (IF) Computable Integer Functions (CF) IF ≟ CF Halting Problem IF ≠ CF Computable Integer Functions (CF)

14. Fall 2004ICOM 4036 Programming Laguages Lecture 2 13 The Halting Problem (Alan Turing 1936) Given a program and an input to the program, determine if the program will eventually stop when it is given that input. Compute Program P Input I P Halts on I? Cannot Build This Want to describe the set of computable functions?

15. Fall 2004ICOM 4036 Programming Laguages Lecture 2 14 Mathematical Computers: The Turing Machine (1936) Alan Turing 01 01 FSM Infinit e I/O TAPE 0/{1,0,R} 1/{0,1,L} Tape Head Next State Write Symbol Head Movement Input Symbol

16. Fall 2004ICOM 4036 Programming Laguages Lecture 2 15 Mathematical Computers: The Turing Machine (1936) Alan Turing 01 01 FSM Infinit eTAPE 0/{1,0,R} 1/{0,1,L} FSM Infinit e I/O TAPE Tape Head Turing demonstrated how to solve several problems using his computing model

17. Fall 2004ICOM 4036 Programming Laguages Lecture 2 16 FSM Sorting TM FSM Sorting TM FSM Sorting TM Ad-hoc Turing Machines FSM Sorting TM FSM Searching TM FSM Integrating TM Can we build a general purpose TM?

18. Fall 2004ICOM 4036 Programming Laguages Lecture 2 17 The Universal Turing Machine (UTM) The Paradigm for Modern General Purpose Computers Universal TM Coded TM MCoded Tape for M Capable of Emulating Every other TM Shown possible by Alan Turing (1936) BIG IDEA: INTEPRETATION!!! Software (flexible) Hardware (fast) Programming = Encoding Algorithms

19. Fall 2004ICOM 4036 Programming Laguages Lecture 2 18 Other Familiar Models of Computation Combinational Circuits Sequential Circuits (FSM’s) Pentium Instruction Set Architectures Lambda Calculus Recursive Functions C++ Can you tell which ones are Turing Universal? That is, which ones can emulate any other Turing Machine?

20. Fall 2004ICOM 4036 Programming Laguages Lecture 2 19 Computing in Perspective CMOS Gate FSM ISA Assembler 1Assembler 2Assembler 3 C++PascalFortran MatLab Build One Build Many Excel Interpreter Design Demands Programming Language Design PSpice All have embedded PL’s

21. Fall 2004ICOM 4036 Programming Laguages Lecture 2 20 Why Abstraction Layers? Resilience to change: –Each layer provides a level of indirection Divide and Conquer Approach: –Can work on one small semantic gap at a time Building Block Approach: –Can build many higher layer on same lower layer Because we know of no other way of doing anything

22. Fall 2004ICOM 4036 Programming Laguages Lecture 2 21 Church’s Thesis Alonso Church “All the models of computation yet developed, and all those that may be developed in the future, are equivalent in power.” “Any realizable computing device can be simulated by a Turing machine” Issues not considered: Size, Programmability, Performance But they must be considered if one is to build …

23. Fall 2004ICOM 4036 Programming Laguages Lecture 2 22 DataPaths PC ABR ALU AC Practical Universal Computers ( John) Von Neumann Architecture (1945) Program Data Memory Control Unit (FSM) CPU CPU is a universal TM An interpreter of some programming language (PL) status control This looks just like a TM Tape

24. Fall 2004ICOM 4036 Programming Laguages Lecture 2 23 Part II - Outline The Von Neumann Architecture From Voltages to Computers Low-level Programming Implementing HLL Abstractions –Control structures –Data Structures –Procedures and Functions

25. Fall 2004ICOM 4036 Programming Laguages Lecture 2 24 The (John) Von Neumann Architecture (late 40’s) I/O devices Central Processing Unit (CPU) Memory Allow communication with outside world Interprets instructions Stores both programs and data After 60 years … most processors still look like this!

26. Fall 2004ICOM 4036 Programming Laguages Lecture 2 25 The von Neumann Architecture Central Processing (CPU) I/O devices Central Processing Unit (CPU) Memory Control Unit (FSM) Data Paths Interconnected registers, muxes, decoders, … controlstatus active passive

27. Fall 2004ICOM 4036 Programming Laguages Lecture 2 26 The (John) Von Neumann Architecture The Memory Unit I/O devices Central Processing Unit (CPU) Memory 0 1ADD A 2SUB B 3JUMP 1 A B … N-1 word size address space

28. Fall 2004ICOM 4036 Programming Laguages Lecture 2 27 The (John) Von Neumann Architecture Stored Program Concept 0 1ADD A 2SUB B 3JUMP 1 A B … N-1 Program Instructions Program Data Programs and their data coexist in memory Processor, under program control, keeps track of what needs to be interpreted as instructions and what as data.

29. Fall 2004ICOM 4036 Programming Laguages Lecture 2 28 Easy I Memory Interface CPU MEMORY address data word memory op {R,W,NOP}

30. Fall 2004ICOM 4036 Programming Laguages Lecture 2 29 Easy I A Simple Accumulator Processor Instruction Set Architecture (ISA) Instruction Format (16 bits) IopcodeX 09101415 I = Indirect bit

31. Fall 2004ICOM 4036 Programming Laguages Lecture 2 30 NameOpcodeAction I=0 Action I=1 Comp 00 000 AC ← not ACAC <- not AC ShR 00 001 AC ← AC / 2 BrN 00 010 AC < 0 ⇒ PC ← XAC < 0 ⇒ PC ← MEM[X] Jump 00 011 PC ← XPC ← MEM[X] Store 00 100 MEM[X] ← ACMEM[MEM[X]] ← AC Load 00 101 AC ← MEM[X]AC ← MEM[MEM[X]] And 00 110 AC ← AC and XAC ← AC and MEM[X] Add 00 111 AC ← AC + XAC ← AC + MEM[X] Easy I A Simple Accumulator Processor Instruction Set Architecture (ISA) Instruction Set Easy all right … but universal it is!

32. Fall 2004ICOM 4036 Programming Laguages Lecture 2 31 Easy I Data Paths (with control points) le ADDRESSBUSADDRESSBUS A0 A bus AB AC PC ALU DATABUSDATABUS DI le op is sel le sel 01 0 1

33. Fall 2004ICOM 4036 Programming Laguages Lecture 2 32 Easy I A Simple Accumulator Processor Instruction Set Architecture (ISA) Accumulator (AC) is implicit operand to many instructions. No need to use instruction bits to specify one of the operands. More bits left for address and opcodes. Although simple, Easy I is universal. (given enough memory). Can you see this? Immediate bit specifies level of indirection for the location of the operand. I = 1: operand in X field (immediate). I=1 operand in memory location X (indirect). Some Immediate Observations on the Easy I ISA

34. Fall 2004ICOM 4036 Programming Laguages Lecture 2 33 Easy I - Control Unit Control Unit Combinational Logic DataPaths + state AC:15 OpCode clock I bit Current State EDB sel PC is DI le AO le AO sel AC le PC sel MEM op ALU op Next State 17 11

35. Fall 2004ICOM 4036 Programming Laguages Lecture 2 34 What makes a CPU cycle? CU Logic FSM logic state Data Paths Logic ALU, latches, memory Cycle time must accommodate signal propagation

36. Fall 2004ICOM 4036 Programming Laguages Lecture 2 35 Easy I – Timing Example ALU Operation AB AC ALU op le DI le CLK DI le DI out ALU out AC le AC out

37. Fall 2004ICOM 4036 Programming Laguages Lecture 2 36 Easy I Control Unit (Level 0 Flowcharts) Fetch Decode Execute Read next instruction Determine what it does and prepare to do it. Fetch operands. Do it! We will ignore indirect bit (assuming I = 0) for now

38. Fall 2004ICOM 4036 Programming Laguages Lecture 2 37 Easy I Control Unit (Level 1 Flowcharts) Fetch AoprSoprLoadStoreJumpBrN Level 1: Each box may take several CPU cycles to execute Reset What?

39. Fall 2004ICOM 4036 Programming Laguages Lecture 2 38 Easy I Control Unit (Level 2 Flowcharts) Each box may take only one CPU cycle to execute 0 → PC reset1 PC → AO PC + 2 → PC reset2 RESET fetch Byte Addressable Can you tell why?

40. Fall 2004ICOM 4036 Programming Laguages Lecture 2 39 Easy I Control Unit (Level 3 Flowcharts) AO → EAB EDB → DI branch on opcode fetch FETCH 00 11x opcode aoprsoprloadstorebrnjump 00 00x00 10000 10100 01000 011 Opcode must be an input to CU’s sequential circuit Invariant At the beginning of the fetch cycle AO holds address of instruction to be fetched and PC points to following instruction Memory Bus Operation

41. Fall 2004ICOM 4036 Programming Laguages Lecture 2 40 Easy I Control Unit (Level 2 Flowcharts) DI → ABUS → ALUA AC → ALUB ALU → AC PC → AO PC + 2 → PC aopr AOpr fetch Restore fetch invariant

42. Fall 2004ICOM 4036 Programming Laguages Lecture 2 41 Easy I Control Unit (Level 2 Flowcharts) AC → ALUB ALU → AC PC → AO PC + 2 → PC sopr SOpr fetch

43. Fall 2004ICOM 4036 Programming Laguages Lecture 2 42 Easy I Control Unit (Level 2 Flowcharts) DI → ABUS → AO load1 DI → ABUS → ALUA ALU → AC PC → AO PC + 2 → PC load2 Load fetch AO → EAB EDB → DI load3

44. Fall 2004ICOM 4036 Programming Laguages Lecture 2 43 Easy I Control Unit (Level 2 Flowcharts) DI → ABUS → AO store1 store2 Store fetch AC → EDB AO → EAB PC → AO PC + 2 → PC

45. Fall 2004ICOM 4036 Programming Laguages Lecture 2 44 Easy I Control Unit (Level 2 Flowcharts) PC → AO PC + 2 → PC brn1 brn2 BrN fetch DI → PC DI → AO PC + 2 → PC AC:15 1 (AC<0) 0 (AC>0) Bit 15 of AC input to the CU’s sequential circuit Assume branch not taken. Allow AC:15 to propagate. Can we accomplish all this in 1 cycle? How?

46. Fall 2004ICOM 4036 Programming Laguages Lecture 2 45 Inside the Easy-I PC +2 Adder ABUS PC 0 pcsel pcis PC capable of loading and incrementing simultaneously 00 011011 0 1 PC

47. Fall 2004ICOM 4036 Programming Laguages Lecture 2 46 Easy I Control Unit (Level 2 Flowcharts) DI → PC DI → AO PC + 2 → PC jump JUMP fetch

48. Fall 2004ICOM 4036 Programming Laguages Lecture 2 47 Easy I Data Paths (with control points) le ADDRESSBUSADDRESSBUS A0 A bus AB AC PC ALU DATABUSDATABUS DI le op is sel le sel 01 0 1

49. Fall 2004ICOM 4036 Programming Laguages Lecture 2 48 Easy I Control Unit State Transition Table (Part I) Curr State opcodeAC:15Next State ALU op Mem OP PC sel PC is DI le AC le AO sel AO le EDB sel reset1xx xxxxreset2XXXNOP01X00X0X reset2xx xxxxfetchXXXNOP1010001X fetch00 00xxsoprXXXNOP11X10X0X fetch00 010xbrn1XXXRD11X10X0X fetch00 011xjumpXXXRD11X10X0X fetch00 100xstore1XXXRD11X10X0X fetch00 101xload1XXXRD11X10X0X fetch00 11xxaoprXXXRD11X10X0X aopr00 110xfetchANDNOP1010101X aopr00 111xfetchADDNOP1010101X sopr00 000xfetchNOTBNOP1010101X sopr00 001xfetchSHRBNOP1010101X

50. Fall 2004ICOM 4036 Programming Laguages Lecture 2 49 Easy I Control Unit State Transition Table (Part II) Current State opcodeAC:15Next State ALU op Mem OP PC sel PC is DI le AC le AO sel AO le EDB sel store1xx xxxxstore2XXXNOP11X0011X store2xx xxxxstore3XXXWR10100011 load1xx xxxxload2XXXNOP11X0011X load2xx xxxxload3XXXRD11X10X0X load3xx xxxxfetchXXXNOP1010101X brn1xx xxx0fetchXXXNOP1010001X brn1xx xxx1brn2XXXNOP1010001X brn2xx xxxxfetchXXXNOP1000011X jumpxx xxxxfetchXXXNOP1000011X CU with 14 states => 4 bits of state This is a (micro)program that interprets machine code

51. Fall 2004ICOM 4036 Programming Laguages Lecture 2 50 Easy-I Control Unit – Some missing details StateEncoding reset1 0000 reset2 0001 fetch 0010 aopr 0011 sopr 0100 store1 0101 store2 0110 store3 0111 load1 1000 load2 1001 load3 1010 brn1 1011 brn2 1100 jump 1101 OperationCodeOutput A000A NOTB001not B AND010A and B ADD011A + B SHRB100B / 2 4-bit Encodings for States ALU Operation Table We know how to implement this ALU ! OperationCode NOP00 ReaD01 WRite10 Control Bus Operation Table

52. Fall 2004ICOM 4036 Programming Laguages Lecture 2 51 Easy I Control Unit State Transition Table (Part I) Curr State opcodeAC:15Next State ALU op Mem OP PC sel PC is DI le AC le AO sel AO le EDB sel 0000xx xxxx0001XXX0001X00X0X 0001xx xxxx0010XXX001010001X 001000 00xx0100XXX0011X10X0X 001000 010x1011XXX0111X10X0X 001000 011x1101XXX0111X10X0X 001000 100x0101XXX0111X10X0X 001000 101x1000XXX0111X10X0X 001000 11xx0011XXX0111X10X0X 001100 110x0010010001010101X 001100 111x0010011001010101X 010000 000x0010001001010101X 010000 001x0010100001010101X

53. Fall 2004ICOM 4036 Programming Laguages Lecture 2 52 Easy I Control Unit State Transition Table (Part II) Current State opcodeAC:15Next State ALU op Mem OP PC sel PC is DI le AC le AO sel AO le EDB sel 0101xx xxxx0110XXX0011X0011X 0110xx xxxx0111XXX10 100011 1000xx xxxx1001XXX0011X0011X 1001xx xxxx1010XXX0111X10X0X 1010xx xxxx0010XXX001010101X 1011xx xxx00010XXX001010001X 1011xx xxx11100XXX001010001X 1100xx xxxx0010XXX001000011X 1101xx xxxx0010XXX001000011X

54. Fall 2004ICOM 4036 Programming Laguages Lecture 2 53 Building the Easy-I C-Unit 2 Approaches Harwired –Apply well known sequential circuit techniques Micro-programmed –Treat state transition table as a program –Build a new abstraction layer The Microprogramming abstraction level A  program

55. Fall 2004ICOM 4036 Programming Laguages Lecture 2 54 Building the Easy-I C-Unit Hardwired Approach ROM state AC:15 DI 10 4 Data Paths Memory Unit control bus address bus data bus next state control point signals 5 Control Unit 11 2

56. Fall 2004ICOM 4036 Programming Laguages Lecture 2 55 Computing Integer Division Iterative C++ Version int a = 12; int b = 4; int result = 0; main () { if (a >= b) { while (a > 0) { a = a - b; result ++; } We ignore procedures and I/O for now

57. Fall 2004ICOM 4036 Programming Laguages Lecture 2 56 Definition Instruction Set Architecture What it is: –The programmers view of the processor –Visible registers, instruction set, execution model, memory model, I/O model What it is not: –How the processors if build –The processor’s internal structure

58. Fall 2004ICOM 4036 Programming Laguages Lecture 2 57 Easy I A Simple Accumulator Processor Instruction Set Architecture (ISA) Instruction Format (16 bits) IopcodeX 09101415 I = Indirect bit

59. Fall 2004ICOM 4036 Programming Laguages Lecture 2 58 Symbolic Name OpcodeAction I=0 Symbolic Name Action I=1 Comp 00 000 AC ← not ACCompAC <- not AC ShR 00 001 AC ← AC / 2ShRAC ← AC / 2 BrN i 00 010 AC < 0 ⇒ PC ← XBrNAC < 0 ⇒ PC ← MEM[X] Jump i 00 011 PC ← XJumpPC ← MEM[X] Store i 00 100 MEM[X] ← ACStoreMEM[MEM[X]] ← AC Load i 00 101 AC ← MEM[X]LoadAC ← MEM[MEM[X]] And i 00 110 AC ← AC and XAndAC ← AC and MEM[X] Add i 00 111 AC ← AC + XAddAC ← AC + MEM[X] Easy I A Simple Accumulator Processor Instruction Set Architecture (ISA) Instruction Set

60. Fall 2004ICOM 4036 Programming Laguages Lecture 2 59 Easy I Memory Model 0 2ADD A 4SUB B 6JUMP 1 A B … 512 8 bits

61. Fall 2004ICOM 4036 Programming Laguages Lecture 2 60 Computing Integer Division Iterative C++ Version int a = 12; int b = 4; int result = 0; main () { if (a >= b) { while (a > 0) { a = a - b; result ++; } Easy-I Assembly Language C++ HLL

62. Fall 2004ICOM 4036 Programming Laguages Lecture 2 61 0:andi 0# AC = 0 addi 12 storei 1000# a = 12 (a stored @ 1000) andi 0# AC = 0 addi 4 storei 1004# b = 4 (b stored @ 1004) andi 0# AC = 0 storei 1008# result = 0 (result @ 1008) Computing Integer Division Iterative C++ Version int a = 12; int b = 4; int result = 0; main () { if (a >= b) { while (a > 0) { a = a - b; result ++; } Translate Data: Global Layout Easy-I Assembly Language C++ HLL Issues Memory allocation Data Alignment Data Sizing

63. Fall 2004ICOM 4036 Programming Laguages Lecture 2 62 Computing Integer Division Iterative C++ Version int a = 12; int b = 4; int result = 0; main () { if (a >= b) { while (a > 0) { a = a - b; result ++; } Translate Code: Conditionals If-Then 0:andi 0# AC = 0 addi 12 storei 1000# a = 12 (a stored @ 1000) andi 0# AC = 0 addi 4 storei 1004# b = 4 (b stored @ 1004) andi 0# AC = 0 storei 1008# result = 0 (result @ 1008) main:loadi 1004# compute a – b in AC comp# using 2’s complement add addi 1 add 1000 brni exit# exit if AC negative exit: Easy-I Assembly Language C++ HLL Issues Must translate HLL boolean expression into ISA-level branching condition

64. Fall 2004ICOM 4036 Programming Laguages Lecture 2 63 Computing Integer Division Iterative C++ Version int a = 12; int b = 4; int result = 0; main () { if (a >= b) { while (a > 0) { a = a - b; result ++; } Translate Code: Iteration (loops) 0:andi 0# AC = 0 addi 12 storei 1000# a = 12 (a stored @ 1000) andi 0# AC = 0 addi 4 storei 1004# b = 4 (b stored @ 1004) andi 0# AC = 0 storei 1008# result = 0 (result @ 1008) main:loadi 1004# compute a – b in AC comp# using 2’s complement add addi 1 add 1000 brni exit# exit if AC negative loop:loadi 1000 brni endloop jump loop endloop: exit: Easy-I Assembly Language C++ HLL

65. Fall 2004ICOM 4036 Programming Laguages Lecture 2 64 Computing Integer Division Iterative C++ Version int a = 12; int b = 4; int result = 0; main () { if (a >= b) { while (a > 0) { a = a - b; result ++; } Translate Code: Arithmetic Ops 0:andi 0# AC = 0 addi 12 storei 1000# a = 12 (a stored @ 1000) andi 0# AC = 0 addi 4 storei 1004# b = 4 (b stored @ 1004) andi 0# AC = 0 storei 1008# result = 0 (result @ 1008) main:loadi 1004# compute a – b in AC comp# using 2’s complement add addi 1 add 1000 brni exit# exit if AC negative loop:loadi 1000 brni endloop loadi 1004# compute a – b in AC comp # using 2’s complement add addi 1 add 1000# Uses indirect bit I = 1 jumpi loop endloop: exit: Easy-I Assembly Language C++ HLL

66. Fall 2004ICOM 4036 Programming Laguages Lecture 2 65 Computing Integer Division Iterative C++ Version int a = 12; int b = 4; int result = 0; main () { if (a >= b) { while (a > 0) { a = a - b; result ++; } Translate Code: Assignments 0:andi 0# AC = 0 addi 12 storei 1000# a = 12 (a stored @ 1000) andi 0# AC = 0 addi 4 storei 1004# b = 4 (b stored @ 1004) andi 0# AC = 0 storei 1008# result = 0 (result @ 1008) main:loadi 1004# compute a – b in AC comp# using 2’s complement add addi 1 add 1000 brni exit# exit if AC negative loop:loadi 1000 brni endloop loadi 1004# compute a – b in AC comp # using 2’s complement add addi 1 add 1000# Uses indirect bit I = 1 storei 1000 jump loop endloop: exit: Easy-I Assembly Language C++ HLL

67. Fall 2004ICOM 4036 Programming Laguages Lecture 2 66 Computing Integer Division Iterative C++ Version int a = 12; int b = 4; int result = 0; main () { if (a >= b) { while (a > 0) { a = a - b; result ++; } Translate Code: Increments 0:andi 0# AC = 0 addi 12 storei 1000# a = 12 (a stored @ 1000) andi 0# AC = 0 addi 4 storei 1004# b = 4 (b stored @ 1004) andi 0# AC = 0 storei 1008# result = 0 (result @ 1008) main:loadi 1004# compute a – b in AC comp# using 2’s complement add addi 1 add 1000 brni exit# exit if AC negative loop:loadi 1000 brni endloop loadi 1004# compute a – b in AC comp # using 2’s complement add addi 1 add 1000# Uses indirect bit I = 1 storei 1000 loadi 1008# result = result + 1 addi 1 storei 1008 jumpi loop endloop: exit: Easy-I Assembly Language C++ HLL

68. Fall 2004ICOM 4036 Programming Laguages Lecture 2 67 Computing Integer Division Easy I Machine Code AddressI BitOpcode (binary) X (base 10) 0000 1100 2000 11112 4000 1001000 6000 1100 8000 1114 10000 1001004 12000 1100 14000 1001008 16000 1011004 18000 000unused 20000 1111 22100 1111000 24000 01046 26000 1011000 28000 01046 30000 1011004 32000 000unused 34000 1111 36000 1001000 38000 1011008 40000 1111 42000 1001008 44000 01126 AddressContents 1000a 1004b 1008result Data Program Challenge Make this program as small and fast as possible

69. Fall 2004ICOM 4036 Programming Laguages Lecture 2 68 The MIPS Architecture ISA at a Glance Reduced Instruction Set Computer (RISC) 32 general purpose 32-bit registers Load-store architecture: Operands in registers Byte Addressable 32-bit address space

70. Fall 2004ICOM 4036 Programming Laguages Lecture 2 69 The MIPS Architecture 32 Register Set (32-bit registers) Register #Reg NameFunction r0 Zero constant r4-r7a0-a3Function arguments r1atReserved for Operating Systems r30fpFrame pointer r28gpGlobal memory pointer r26-r27k0-k1Reserved for OS Kernel r31raFunction return address r16-r23s0-s7Callee saved registers r29spStack pointer r8-r15t0-t7Temporary variables r24-r25t8-t9Temporary variables r2-r3v0-v1Function return values

71. Fall 2004ICOM 4036 Programming Laguages Lecture 2 70 Simple and uniform 32-bit 3-operand instruction formats –R Format: Arithmetic/Logic operations on registers –I Format: Branches, loads and stores –J Format: Jump Instruction The MIPS Architecture Main Instruction Formats opcode 6 bits rs 5 bits rt 5 bits rd 5 bits shamt 5 bits funct 6 bits opcode 6 bits rs 5 bits rt 5 bits Address/Immediate 16 bits opcode 6 bits rs 5 bits rt 5 bits Address/Immediate 16 bits

72. Fall 2004ICOM 4036 Programming Laguages Lecture 2 71 The MIPS Architecture Examples of Native Instruction Set Instruction Group InstructionFunction Arithmetic/ Logic add $s1,$s2,$s3$s1 = $s2 + $s3 addi $s1,$s2,K$s1 = $s2 + K Load/Storelw $s1,K($s2)$s1 = MEM[$s2+K] sw $s1,K($s2)MEM[$s2+K] = $s1 Jumps and Conditional Branches beq $s1,$s2,Kif ($s1=$s2) goto PC + 4 + K slt $s1,$s2,$s3if ($s2<$s3) $s1=1 else $s1=0 j Kgoto K Proceduresjal K$ra = PC + 4; goto K jr $ragoto $ra

73. Fall 2004ICOM 4036 Programming Laguages Lecture 2 72 The SPIM Assembler Examples of Pseudo-Instruction Set Instruction Group SyntaxTranslates to: Arithmetic/ Logic neg $s1, $s2sub $s1, $r0, $s2 not $s1, $s2nor $17, $18, $0 Load/Storeli $s1, Kori $s1, $0, K la $s1, Klui $at, 152 ori $s1, $at, -27008 move $s1, $s2 Jumps and Conditional Branches bgt $s1, $s2, Kslt $at, $s1, $s2 bne $at, $0, K sge $s1, $s2, $s3 bne $s3, $s2, foo ori $s1, $0, 1 beq $0, $0, bar foo: slt $s1, $s3, $s2 bar: Pseudo Instructions: translated to native instructions by Assembler

74. Fall 2004ICOM 4036 Programming Laguages Lecture 2 73 The SPIM Assembler Examples of Assembler Directives GroupDirectiveFunction Memory Segmentation.data Data Segment starting at.text Text (program) Segment.stack Stack Segment.ktext Kernel Text Segment.kdata Kernel Data Segment Data Allocationx:.word Allocates 32-bit variable x:.byte Allocates 8-bit variable x:.ascii “hello”Allocates 8-bit cell array Other.globl xx is external symbol Assembler Directives: Provide assembler additional info to generate machine code

75. Fall 2004ICOM 4036 Programming Laguages Lecture 2 74 Handy MIPS ISA References Appendix A: Patterson & Hennessy SPIM ISA Summary on class website Patterson & Hennessy Back Cover

76. Fall 2004ICOM 4036 Programming Laguages Lecture 2 75 The MIPS Architecture Memory Model 32-bit byte addressable address space

77. Fall 2004ICOM 4036 Programming Laguages Lecture 2 76 Computing Integer Division Iterative C++ Version int a = 12; int b = 4; int result = 0; main () { while (a >= b) { a = a - b; result ++; } MIPS/SPIM Version MIPS Assembly Language C++.data# Use HLL program as a comment x:.word12# int x = 12; y:.word4# int y = 4; res:.word0# int res = 0;.globlmain.text main:la$s0, x# Allocate registers for globals lw$s1, 0($s0)# x in $s1 lw$s2, 4($s0)# y in $s2 lw$s3, 8($s0)# res in $s3 while:bgt$s2, $s1, endwhile# while (x >= y) { sub$s1, $s1, $s2# x = x - y; addi$s3, $s3, 1# res ++; jwhile# } endwhile: la$s0, x# Update variables in memory sw$s1, 0($s0) sw$s2, 4($s0) sw$s3, 8($s0)

78. Fall 2004ICOM 4036 Programming Laguages Lecture 2 77 Computing Integer Division Iterative C++ Version int a = 12; int b = 4; int result = 0; main () { while (a >= b) { a = a - b; result ++; } printf("Result = %d \n"); } MIPS/SPIM Version Input/Output in SPIM MIPS Assembly Language C++.data# Use HLL program as a comment x:.word12# int x = 12; y:.word4# int y = 4; res:.word0# int res = 0; pf1:.asciiz "Result = ".globlmain.text main:la$s0, x# Allocate registers for globals lw$s1, 0($s0)# x in $s1 lw$s2, 4($s0)# y in $s2 lw$s3, 8($s0)# res in $s3 while:bgt$s2, $s1, endwhile# while (x >= y) { sub$s1, $s1, $s2# x = x - y; addi$s3, $s3, 1# res ++; jwhile# } endwhile: la$a0, pf1# printf("Result = %d \n"); li$v0, 4# //system call to print_str syscall move$a0, $s3 li$v0, 1# //system call to print_int syscall la$s0, x# Update variables in memory sw$s1, 0($s0) sw$s2, 4($s0) sw$s3, 8($s0)

79. Fall 2004ICOM 4036 Programming Laguages Lecture 2 78 SPIM Assembler Abstractions Symbolic Labels –Instruction addresses and memory locations Assembler Directives –Memory allocation –Memory segments Pseudo-Instructions –Extend native instruction set without complicating arquitecture Macros