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SYEN 3330 Digital SystemsJung H. Kim 1 SYEN 3330 Digital Systems Chapter 7 – Part 2
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SYEN 3330 Digital Systems Chapter 7-2 Page 2 Counters
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SYEN 3330 Digital Systems Chapter 7-2 Page 3 Counter Basics: Divide by 2
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SYEN 3330 Digital Systems Chapter 7-2 Page 4 Divide Clock Frequency by 2
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SYEN 3330 Digital Systems Chapter 7-2 Page 5 Ripple Counter
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SYEN 3330 Digital Systems Chapter 7-2 Page 6 Ripple Counter (Continued)
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SYEN 3330 Digital Systems Chapter 7-2 Page 7 Ripple Counter (Continued)
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SYEN 3330 Digital Systems Chapter 7-2 Page 8 Ripple Counter (Continued)
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SYEN 3330 Digital Systems Chapter 7-2 Page 9 Ripple Counter (Continued)
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SYEN 3330 Digital Systems Chapter 7-2 Page 10 Ripple Counter (Continued)
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SYEN 3330 Digital Systems Chapter 7-2 Page 11 Ripple Counter (Continued)
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SYEN 3330 Digital Systems Chapter 7-2 Page 12 Synchronous Counters
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SYEN 3330 Digital Systems Chapter 7-2 Page 13 Synchronous Counters (Continued)
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SYEN 3330 Digital Systems Chapter 7-2 Page 14 Synchronous Counters (Continued)
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SYEN 3330 Digital Systems Chapter 7-2 Page 15 Synchronous Counters – Serial Gating When a two-input AND gate is used for each stage of the counter with a “ripple- like” carry, this is referred to as serial gating. As the size of the counter increases the delay through the combinational logic increases roughly in proportion to n, the number of stages.
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SYEN 3330 Digital Systems Chapter 7-2 Page 16 Synchronous Counters – Parallel Gating When a multiple-input ( >2) AND gates are used for each stage of the counter with logic dedicated to each stage or to a group of stages, this is referred to as parallel gating. It resembles carry lookahead in an adder. As the size of the counter increases the delay through the combinational logic increases roughly in proportion to n/m, the number of stages/the group size.
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SYEN 3330 Digital Systems Chapter 7-2 Page 17 Design: Synchronous BCD
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SYEN 3330 Digital Systems Chapter 7-2 Page 18 Synchronous BCD (Continued) Use K-Maps to minimize the next state function:
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SYEN 3330 Digital Systems Chapter 7-2 Page 19 Synchronous BCD (Continued) The minimized circuit:
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SYEN 3330 Digital Systems Chapter 7-2 Page 20 Synchronous BCD (Continued)
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SYEN 3330 Digital Systems Chapter 7-2 Page 21 Synchronous BCD (Continued)
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SYEN 3330 Digital Systems Chapter 7-2 Page 22 Synchronous BCD (Continued)
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SYEN 3330 Digital Systems Chapter 7-2 Page 23 Counter with Parallel Load
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SYEN 3330 Digital Systems Chapter 7-2 Page 24 Counting Modulo N
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SYEN 3330 Digital Systems Chapter 7-2 Page 25 Counting Modulo 7 IN 8 Q8Q8 IN 4 Q4Q4 IN 2 Q2Q2 IN 1 Q1Q1 CLEAR CP LOAD CLOCK "0" "1"
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SYEN 3330 Digital Systems Chapter 7-2 Page 26 Counting Modulo 7, Preset 9 CLOCK "1" IN 8 Q8Q8 IN 4 Q4Q4 IN 2 Q2Q2 IN 1 Q1Q1 CLEAR CP LOAD "0" "1"
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SYEN 3330 Digital Systems Chapter 7-2 Page 27 Timing Sequences
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SYEN 3330 Digital Systems Chapter 7-2 Page 28 Counter Decoder Example
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SYEN 3330 Digital Systems Chapter 7-2 Page 29 Ring Counter
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SYEN 3330 Digital Systems Chapter 7-2 Page 30 Johnson Counter (Switch-Tail) BCBC
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SYEN 3330 Digital Systems Chapter 7-2 Page 31 Verilog for Registers and Counters Register – same as flip-flop except multiple bits: reg[3:0] Q; input[3:0] D; always@(posedge CLK or posedge RESET) begin if (RESET)Q <= 4'b0000; else Q <= D; end Shift Register – use concatenate: Q <= {Q[2:0], SI}; Counter – use increment/decrement: count <= count + 1; or count <= count - 1
![SYEN 3330 Digital Systems Chapter 7-2 Page 31 Verilog for Registers and Counters Register – same as flip-flop except multiple bits: reg[3:0] Q; input[3:0] D; CLK or posedge RESET) begin if (RESET)Q <= 4 b0000; else Q <= D; end Shift Register – use concatenate: Q <= {Q[2:0], SI}; Counter – use increment/decrement: count <= count + 1; or count <= count - 1](http://images.slideplayer.com./31/9716559/slides/slide_31.jpg "SYEN 3330 Digital Systems Chapter 7-2 Page 31 Verilog for Registers and Counters Register – same as flip-flop except multiple bits: reg[3:0] Q; input[3:0] D; CLK or posedge RESET) begin if (RESET)Q <= 4 b0000; else Q <= D; end Shift Register – use concatenate: Q <= {Q[2:0], SI}; Counter – use increment/decrement: count <= count + 1; or count <= count - 1")
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SYEN 3330 Digital Systems Chapter 7-2 Page 32 Verilog Description of Left Shift Register // 4-bit Shift Register with Reset // (See Figure 5-3) module srg_4_r_v (CLK, RESET, SI, Q,SO); input CLK, RESET, SI; output [3:0] Q; output SO; reg [3:0] Q; assign SO = Q[3]; always@(posedge CLK or posedge RESET) begin if (RESET) Q <= 4'b0000; else Q <= {Q[2:0], SI}; end endmodule
![SYEN 3330 Digital Systems Chapter 7-2 Page 32 Verilog Description of Left Shift Register // 4-bit Shift Register with Reset // (See Figure 5-3) module srg_4_r_v (CLK, RESET, SI, Q,SO); input CLK, RESET, SI; output [3:0] Q; output SO; reg [3:0] Q; assign SO = Q[3]; CLK or posedge RESET) begin if (RESET) Q <= 4 b0000; else Q <= {Q[2:0], SI}; end endmodule](http://images.slideplayer.com./31/9716559/slides/slide_32.jpg "SYEN 3330 Digital Systems Chapter 7-2 Page 32 Verilog Description of Left Shift Register // 4-bit Shift Register with Reset // (See Figure 5-3) module srg_4_r_v (CLK, RESET, SI, Q,SO); input CLK, RESET, SI; output [3:0] Q; output SO; reg [3:0] Q; assign SO = Q[3]; CLK or posedge RESET) begin if (RESET) Q <= 4 b0000; else Q <= {Q[2:0], SI}; end endmodule")
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SYEN 3330 Digital Systems Chapter 7-2 Page 33 Verilog Description of Binary Counter // 4-bit Binary Counter with Reset // (See Figure 5-10) module count_4_r_v (CLK, RESET, EN, Q, CO); input CLK, RESET, EN; output [3:0] Q; output CO; reg [3:0] count; assign Q = count; assign CO = (count == 4'b1111 && EN == 1'b1) ? 1 : 0; always@(posedge CLK or posedge RESET) begin if (RESET) count <= 4'b0; else if (EN) count <= count + 1; end endmodule
![SYEN 3330 Digital Systems Chapter 7-2 Page 33 Verilog Description of Binary Counter // 4-bit Binary Counter with Reset // (See Figure 5-10) module count_4_r_v (CLK, RESET, EN, Q, CO); input CLK, RESET, EN; output [3:0] Q; output CO; reg [3:0] count; assign Q = count; assign CO = (count == 4 b1111 && EN == 1 b1) .](http://images.slideplayer.com./31/9716559/slides/slide_33.jpg "1 : 0; CLK or posedge RESET) begin if (RESET) count <= 4 b0; else if (EN) count <= count + 1; end endmodule.")
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