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LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland1 Production of the LHCb Silicon Tracker Readout Electronics.

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Presentation on theme: "LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland1 Production of the LHCb Silicon Tracker Readout Electronics."— Presentation transcript:

1 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland1 Production of the LHCb Silicon Tracker Readout Electronics

2 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland2 Outline  Overview of the Readout Electronics  1st preproduction of Digitizer Board  Evaluation of performance  Integration with LHCb hardware  2nd preproduction  Conclusion

3 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland3 LHCb Silicon Tracker principle  Two distinct tracking systems based on silicon strip detectors, read out via the BEETLE chip  TT: full acceptance angle covered upstream of magnet  IT: only area of highest track densities around beampipe

4 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland4 Beetle readout chip  128 channel charge integrator  polyimide readout hybrid carries 3 (IT) or 4 (TT) Beetle chips for sensors of 384 (IT) or 512 (TT) strips See also:  Talk of F. Lehner: Hybrid Design, Procurement and Testing for the LHCb Silicon Tracker

5 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland5 ST Readout electronics

6 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland6 Service Box Overview Digitizer Board backplane low-voltage power sensor + readout hybrids Digitizer Board up to 16 hybrids/boards Control Card TTCECS 5m copper cable Optical fibres for physics data

7 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland7 Digitizer Board characteristics  6 layer PCB, halogen-free, 1.6 mm thickness, symmetric stack  single side mounting, no buried/blind vias  smallest feature size 6 mil, smallest package 0603  5 BGA devices: 1x CS49 (0.8 mm pitch), 3-4x BGA144(1.0 mm pitch)  no JTAG chain, no boundary scan  differential traces have controlled impedance/length  standard commercial connectors  NO tuning points  layout optimized for low-cost, high-yield, easy testing 2 versions: Trigger Tracker (4-chip readout), Inner Tracker (3-chip readout)

8 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland8 1. Preproduction run  17 boards produced and electrically tested in late 2004 (TT version)  after assembly, all BGAs X-rayed: all solder joints ok!  2 bugfixes: wrong reference voltage for line receiver Auto-Sync FPGA: shift register one cycle (25ns) too short  all boards except one immediately working: board #10 had ripped via under BGA (fixed) changes for IT version preproduction (and final production):  changed VCSEL biasing  added QPLL RC-network for improved jitter stability

9 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland9 Digitizer Board  Power <5 W  Only positive voltages: 2.5 V, 5.0 V

10 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland10 Beetle signal at ADC  Flat top 15 nsec wide (of 25 nsec max.)  measured with 5m twisted pair cable  plenty of ‘space’ to set ADC sampling point

11 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland11 Linearity

12 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland12 Sampling synchronicity I  supply all 16 inputs with ‘synchronous’ testpulse: testpulse generator sourcing 16 LVDS drivers  move sampling time by using TTCrx clock phase shifters (just like in experiment..)  transmit data via GOL+ optical fibres to DACs and scope  record pulseheight of sampled edge vs. programmed delay

13 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland13 Sampling synchronicity II

14 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland14 GOL VCSEL connection  VCSEL forward voltage with 2.5V anode voltage results in too low GOL current driver voltage level  only 2.5V and 5V available  reduced to 3.3V by low-impedance divider  blocked at VCSEL with 100nF||100pF

15 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland15 Eye diagram after 100m  Thanks to Paolo Ciambrone/LHCb Muon

16 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland16 Auto-sync  Beetle DataValid signal (almost) in parallel to analogue data to frame a triggered event  done via shift register in Actel antifuse FPGA (small version of rad-hard AX54SX32) incl. TMR+ majority voting  Results in at least one IDLE frame per event Beetle analogue output Beetle DataValid Beetle data after digitization DataValid after 200 ns delay

17 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland17 Radiation qualification  Expected radiation levels for Service Box location for 10 years: TID 15 krad, NIEL 2E12 n/cm2  all commercial devices individually radiation qualified (TID, NIEL and SEE) with proton and neutron irradiation according to LHCb radiation policy  System test: TT Digitizer Board + backplane re-tested in June 2005 with 60 MeV protons to 60 krad (PSI, Switzerland):  analogue test pattern injected  verification of function and performance  no variations in module operation observed

18 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland18 Full Readout test

19 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland19 Full Readout test  LHCb-style readout (except LHCb Readout Supervisor + CPU farm)

20 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland20 Control Card  Under development by Universidade de Santiago de Compostela  Provides TTC signals and slow control interface to each Service Box and its associated frontend electronics  First prototype functional (still being tested)

21 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland21 Breaking News: IT version  10 Digitizer Boards (IT version preproduction) were delivered last Wednesday  initial testing confirm out-of-the-box functionality  important step: re-validate eye diagram with new VCSEL bias!

22 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland22 Next steps  detailed testing of IT prototypes: last design verification  launch production order after:  production+assembly time for all boards: ca. 8-10 weeks  all parts available except for VCSELs (LHCb common order placed, expected in November)  ‘bird-food’ supplied by company, special components by us  start setting up test bench during production: basic functionality test (go-nogo) burn-in test (catch infant mortality)

23 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland23 Conclusion + Outlook  The preseries production for both versions of the ST Digitizer Board has been completed.  Bugfixes and lessons learned in the TT version were successfully included in the IT version.  Required functionality was verified and system compatibility with common LHCb hardware has been shown.  Preseries hardware is used to form teststands for the TT sensor module production (Zuerich) and the IT sensor production (CERN)  Final qualification pending, design will be released for full production in Q4/05.

24 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland24 SPARE SLIDES

25 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland25 Digitizer Board input stage  Bandwidth: 1.6 kHz (AC-Coupling) to 170 MHz (AD8129)  Amplifier output range matches ADC input range 3x 1 k  22  39  2.5 V 2x 100 nF 8 bits + - gain: 11 differential signal from Beetle AD8129 TSA0801 gain: 0.22 impedance: 100 Ohm 100 nF 10 k  V cm V ref (ca. 1 V) out Output to GOL serializer

26 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland26 Clock tree

27 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland27 TFC distribution  Impedance controlled traces for LVDS signals  TTL traces only used for short (~ 2 cm) for fanning out  equal trace lengths to minimize ch-ch skew

28 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland28 Service Box: frame  Fully loaded weight: ca. 10 kg  Power disipation: ca. 150 W (70 W into mixed water cooled heatsink)

29 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland29 Service Box cooling  all linear regulators located close to each other  use common copper heatsink (mixed water) to cool all at once  isolate ground slug of regulator package (local ground!)  used for testing: CPU water cooling system: no active cooler, but fan-blown heat-exchanger  Test at full load results in 35 degC case temperature for 25 degC water (=ambient temperature)

30 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland30 IT mounting  Service Boxes outside acceptance  Mounted on common IT station frame  ‘5m copper cables’ no not move  cables from Service Box away from detector move (cable chains)

31 LECC 2005, HeidelbergA. Vollhardt, EPF Lausanne/Switzerland31 TT mounting  Service Boxes mounted outside acceptance to magnet  ‘5m copper cable’ guided in cable chains to station halves  cables away from Service Box fixed in cable trays


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