1. May 06-14 FPGA Controlled Amplifier Module (FCAM) December 8, 2005

2. Project Team Information Team Members  Jesse Bartley, CprE  JiWon Lee, EE  Michael Hayen, CprE  Zhi Gao, EE Advisor  Dr. Chris Chu Client  Teradyne Corporation

3. Acknowledgement Teradyne Corporation  Jacob Mertz  Ramon De La Cruz  Steven Miller Additional Help  Jason Boyd  Dr. Randy Geiger

4. Presentation Outline Introductory Materials Technical Overview  Amplifier  DC offset correction Test Plan  Amplifier  DC offset correction Closing Summary

5. Purpose & Tasks of the Project Purpose:  To complete and test the FPGA controlled Amplifier for PC based Spectrum Analyzer developed by Teradyne Main Tasks for this team:  Understand existing design  Board assembly and bring-up  Make detailed test plan  Perform and document tests

6. Intended Users & Uses The primary users:  Engineers of the Teradyne Corporation  A possibility that a derivative of the device will be used outside Teradyne in the future. The product function:  As a pre-amplifier for the signal input to a PC based spectrum analyzer device.  PC based spectrum analyzer was design by previous phase

7. Assumptions The end product will not be sold to other companies. The design specifications previously provided by Teradyne are correct. The design provided by the previous team is valid. Necessary equipment will be available.

8. End Product & Other Deliverables A fully functional and tested design A functioning prototype Complete test plans A full test report Technical documentation on the design.

9. Technical Overview

10. Circuit Overview

11. Two Stage Op-Amp

12. Two Stage Op-Amp Overview Vi - + R3 Vo - + R1

13. Origin of Design Design from Dr. Geiger  Amplifier with Maximum Bandwidth, Randall LGeiger IEEE, Operational Amplifier,1970 Minimizing in-Band Harmonics at Higher Frequencies, http://seniord.ee.iastate.edu/may0528/01084375.pdf Chosen by Phase III, May03-10 Reason:  Very Wide Bandwidth

15. DC-Offset Correction

16. DC-Offset Correction Overview

17. FPGA Offset Calculation Successive Approximation Register Input: Comparator output Checks input, either +/- V Increments output voltage by +/-38μV accordingly Will wait for new comparator output, exact time to be determined based on SPICE simulations.

18. Attenuator Output range of DAC: 0-2.5V Maximum offset of amplifier: -20mV-20mV Conversion circuit:

19. Testing and Verification

20. Testing Design Amplifier Testing  Gao, JiWon DC-Offset Correction Testing  Jesse, Michael Further Constraints  LabVIEW will be used for automated testing  Extra caution will be taken to avoid damage from ESD (Electro-Static Discharge)

21. List of Tests Amplifier testing  PSPICE Simulation Test  Amplifier Gain Test  Harmonic Distortion Test  Amplifier Gain Flatness and Bandwidth Test DC Offset Testing  VHDL Behavior Test  DAC Control Test  Offset Calibration Test  Offset Correction Verification Test

22. Amplifier Testing

23. PSPICE Simulation Test Purpose:  Verification to the design  Assistance to testing Simulation:  Verify design of the amplifier  Determine specifications for gain flatness test  Simulate testing conditions

24. Amplifier Gain Tests Purpose: Ensure the gain requirement of the amplifier over the specification range Methodology:107 testing points covering the whole rang of the Specification  10 frequency ranges  3 input ranges  4 gain settings

25. Circuit Parameters Input VoltageAvailableMax Output FrequencyRangeGain SettingsVoltage Range(Volts)(dB)(Volts) DC – 1kHz+/- 5 volts6, 20, 40, 60+/- 10 volts > 1kHz - 20 kHz+/- 5 volts6, 20, 40, 60+/- 10 volts > 20kHz – 100kHz+/- 2.5 volts6, 20, 40+/- 5 volts > 100kHz – 1MHz+/- 2.5 volts6, 20, 40+/- 5 volts > 1MHz – 10MHz+/- 2.5 volts6, 20, 40+/- 5 volts > 10MHz – 20MHz+/- 2.5 volts6, 20+/- 5 volts > 20MHz – 50MHz+/- 1.0 volts6, 20+/- 2.0 volts > 50MHz – 100MHz+/- 1.0 volts6, 20+/- 2.0 volts

26. Test Circuit Signal Generator LPFAmplifier Circuit (Optional) Multi-Meter 107 input signals will be applied LabVIEW automated ESD Protected

27. Harmonic Distortion Test Purpose: Test the purity of the output signals from the amplifier Methodology:  High and low point and two end frequencies  Mid-band frequency at middle frequency ranges  10 testing points in total Specification: The specified parameters are listed in the next couple of slides

28. Total Harmonic Distortion It is an important measure of the purity of the output of the amplifier.

29. Specified Harmonic Distortion Total InputHarmonic FrequencyDistortion Range(dB) DC – 1kHz< - 105 dB > 1kHz - 20 kHz< - 95 dB > 20kHz – 100kHz< -85 dB > 100kHz – 1MHz< - 80 dB > 1MHz – 10MHz< - 70 dB > 10MHz – 20MHz< -65 dB > 20MHz – 50MHz< -50 dB > 50MHz – 100MHz< -40 dB

30. Test Circuit Signal Generator LPFAmplifier Circuit (Optional) Spectrum Analyzer Signal at mid- point of each frequency range Amplitudes at certain frequency points should be observed and used to calculate the distortion

31. Amplifier Gain Flatness Test Purpose: Ensure the gain flatness requirement of the amplifier  Bandwidth  Gain flatness Criteria:  Provide stable gain within frequency range  Maintain performance at high frequency Key equipment: Spectrum Analyzer Specification: Will be determined by SPICE simulations

32. DC-Offset Testing

33. DC-Offset Correction Tests Simulations with Altera’s Quartus II  Simulate and verify VHDL code Verify FPGA behavior  VHDL code matches design  Plays correctly with other components  Performs intended function within spec

34. DC Offset Specs Important Specifications  Correction to within 1mV  Correct offsets between +20mV and -20mV  Perform calibration within specified time To be determined based on SPICE simulations

35. VHDL Behavior Test Verify that code works as intended Test fixture  Will simulate analog component of circuit Greater than/less than input Propagation delay  Calibrates for DAC output value (0-65536) Give fixture a number in this range, and the DC-offset correction should calibrate to correct that value of offset. Criteria  Correct calibration  Calibration time within spec

36. DAC Control Test Verify DAC and its FPGA control Test Fixture  Uses DAC control module to set DAC output Sweep range of outputs  Increments of 1mV (40 data points) Criteria  Covers range of +/-20mV  Ensure output is linear

37. Offset Calibration Test Verify entire calibration system Provide range of DC input voltages  Cover +25mV to -25mV  Calibrate for each voltage  Measure calibrated output  Time the calibration Criteria  (+/-20mV range) Calibrated output within +/-1mV of ground  (outside +/-20mV) Calibrated output within +/-1mV of maximum corrected value.

38. Offset Correction Verification Final verification of DC-offset calibration with an AC input signal. Range of DC offsets will be artificially injected, forcing correction circuitry to cover its full DC offset (+/-20mV).  Calibrate DC offset for each  Measure calibrated output  Provide a range of AC inputs will be provided, covering (0 – 100Mhz)  Measure average output voltage Criteria:  Average output must remain within +/-1mV of ground after calibration

39. Closing Summary This Team’s Tasks  Assemble the prototype  Develop FPGA code  Test the product  Document all details of the process Project will make contribution  Teradyne  Integrated circuit industry The team will received the following benefits:  Technical knowledge  Team work  Real industry project Overall, this project will benefit both the client and the team

40. Questions