Presentation is loading. Please wait.

Presentation is loading. Please wait.

Ontogenetic hardware Ok, so the Tom Thumb algorithm can self- replicate an arbitrary structure within an FPGA But what kind of structures is it interesting.

Published byPatience Pope Modified over 9 years ago

Similar presentations

Presentation on theme: "Ontogenetic hardware Ok, so the Tom Thumb algorithm can self- replicate an arbitrary structure within an FPGA But what kind of structures is it interesting."— Presentation transcript:

1 Ontogenetic hardware Ok, so the Tom Thumb algorithm can self- replicate an arbitrary structure within an FPGA But what kind of structures is it interesting to self- replicate

2 Ontogenetic hardware Embryonics = embryonic electronics: Drawing inspiration from growth processes of living organisms to design complex computing systems Phylogeny (P) [Evolvability] Epigenesis (E) [Adaptability] Ontogeny (O) [Scalability] PO hw POE hw OE hw PE hw

3 Bio-Inspired Approaches Growth Self-organization Massive parallelism (multicellular systems) Issues that growth can potentially address: Complexity Scalability Fault tolerance

4 Caenorhabditis Elegans 11 December 1998

5 Caenorhabditis Elegans From S.F. Gilbert, Developmental Biology, Sinauer, 1991

6 Multicellular Organization 959 somatic cells

7 Cellular Differentiation Pharynx Intestine

8 Embryonics: How? Iterative electronic circuit based on 3 features: multicellular organization cellular division cellular differentiation

9 Embryonics Landscape Population level (population =  organisms) Organismic level (organism =  cells) Cellular level (cell =  molecules) Molecular level (basic FPGA's element)

10 StopWatch

11

12 Multicellular Organization

13 StopWatch

14 First step: design of a totipotent cell (stem cell) (of course, in practice it can be optimized)

15 StopWatch

16 Cellular Differentiation

17 Cloning

18

19 Self-Repair

20 BioWatch The application can of course be anything… But then, the size and structure of the cell will vary from application to application: we need programmable logic!

21 MUXTREE Molecule The “molecular” layer of Embryonics is an FPGA

22 Cellular Self-Replication But if we use FPGAs, then we need to CREATE the array of cells in the first place, before differentiation can take place (self-replication)

23 Cellular Self-Replication But if we use FPGAs, then we need to CREATE the array of cells in the first place, before differentiation can take place (self-replication)

24 Cellular Self-Replication But if we use FPGAs, then we need to CREATE the array of cells in the first place, before differentiation can take place (self-replication)

25 Cellular Self-Replication Self-replication will allow the same FPGA partial configuration to be duplicated as many times as needed

26 Cellular Self-Repair But self-replication, and custom FPGAs, can ALSO be used to improve the reliability of the system

27 Cellular Self-Repair But self-replication, and custom FPGAs, can ALSO be used to improve the reliability of the system … within limits

28 Operation of the Cell

29 Kill a Molecule

30 Recovered Molecule

31 Kill Again (Kill a Cell)

32 Recovered Cell

33 Implementation - The BioWall

34

35 Genotype Layer Phenotype Layer Example – Automatic Synthesis Application-specific (parallel) functions Developmental algorithm Genetic code Mapping Layer

36 Example – Automatic Synthesis Phenotype Layer Mapping Layer Genotype Layer Totipotent Cell

37 Example – Automatic Synthesis Totipotent Cell Programmable Logic

38 Example – Automatic Synthesis Programmable Logic Cellular Array

39 What kind of applications can take advantage of this kind of system? Complex "real-world" streaming applications computation is carried out sequentially can be represented by a DAG of computation nodes each node processes data locally then forwards them to the next node in the graph Applications ×+÷≠ FFT + × DCT INOUT

40 READDCTQNTZCMPRWRT Example: JPEG Specialized MOVE functional units can be designed for each of these steps INOUT

41 Programmable substrate ×+÷≠ FFT + × DCT Context INOUT Problem: task or resource allocation – i.e. how do we map the graph nodes to the array? Specifically: dynamic allocation

42 Self-Scaling Stream Processing Source Funct A Funct B Funct CJoinFunct A Funct C Funct A Funct C Funct A Funct C

43

44 SSSP The MJPEG application consists of a four-stage computation pipeline. The data to be compressed are composed of 192 bytes corresponding to an 8x8 array of pixels using 24- bit colour. The maximum rate achievable (determined by the input rate) is of 700 packets per second - roughly 1 MBit/second. With a single pipeline, the performance tops at about 60 packets per second.

45

46 SSSP When performance peaks, the average output rate is of 675 packets per second (out of a maximum of 700): this technique allows to multiply the throughput by a factor of 11 using 28 processors.

Download ppt "Ontogenetic hardware Ok, so the Tom Thumb algorithm can self- replicate an arbitrary structure within an FPGA But what kind of structures is it interesting."

Similar presentations

Professur für Technische Informatik A Self Distributing Virtual Machine for FPGA Multicores Klaus Waldschmidt J. W. Goethe-University Technische Informatik.

Professur für Technische Informatik A Self Distributing Virtual Machine for FPGA Multicores Klaus Waldschmidt J. W. Goethe-University Technische Informatik.
Optimization of Parallel Task Execution on the Adaptive Reconfigurable Group Organized Computing System Presenter: Lev Kirischian Department of Electrical.

Optimization of Parallel Task Execution on the Adaptive Reconfigurable Group Organized Computing System Presenter: Lev Kirischian Department of Electrical.
Department of Electronic Engineering NUIG Direct Evolution of Patterns using Genetic Algorithms By: John Brennan Supervisor: John Maher.

Department of Electronic Engineering NUIG Direct Evolution of Patterns using Genetic Algorithms By: John Brennan Supervisor: John Maher.
Daniel Mange Towards Robust Bio-Inspired Circuits: The Embryonics Approach ECAL’99, Lausanne September 15, 1999.

Daniel Mange Towards Robust Bio-Inspired Circuits: The Embryonics Approach ECAL’99, Lausanne September 15, 1999.
Multi-cellular paradigm The molecular level can support self- replication (and self- repair). But we also need cells that can be designed to fit the specific.

Multi-cellular paradigm The molecular level can support self- replication (and self- repair). But we also need cells that can be designed to fit the specific.
Presenter MaxAcademy Lecture Series – V1.0, September 2011 Stream Scheduling.

Presenter MaxAcademy Lecture Series – V1.0, September 2011 Stream Scheduling.
Implementation Approaches with FPGAs Compile-time reconfiguration (CTR) CTR is a static implementation strategy where each application consists of one.

Implementation Approaches with FPGAs Compile-time reconfiguration (CTR) CTR is a static implementation strategy where each application consists of one.
Artificial Neural Network

Artificial Neural Network
Embryonics: A New Methodology for Designing Field-Programmable Gate Arrays with Self-Repair and Self-Replicating Properties Laboratory for Reliable Computing.

Embryonics: A New Methodology for Designing Field-Programmable Gate Arrays with Self-Repair and Self-Replicating Properties Laboratory for Reliable Computing.
SOAR Processing with Field Programmable Gate Arrays Presented by Matthew Scarpino Hoplite Systems LLC.

SOAR Processing with Field Programmable Gate Arrays Presented by Matthew Scarpino Hoplite Systems LLC.
Applications of Systolic Array FTR, IIR filtering, and 1-D convolution. 2-D convolution and correlation. Discrete Furier transform Interpolation 1-D and.

Applications of Systolic Array FTR, IIR filtering, and 1-D convolution. 2-D convolution and correlation. Discrete Furier transform Interpolation 1-D and.
Evolvable Hardware. 2 EWH EHW:  A bio-inspired technique for hardware design. Living beings:  DNA constitute the encoding of every living being on the.

Evolvable Hardware. 2 EWH EHW:  A bio-inspired technique for hardware design. Living beings:  DNA constitute the encoding of every living being on the.
A High Performance Application Representation for Reconfigurable Systems Wenrui GongGang WangRyan Kastner Department of Electrical and Computer Engineering.

A High Performance Application Representation for Reconfigurable Systems Wenrui GongGang WangRyan Kastner Department of Electrical and Computer Engineering.
Bio-inspiration-1/PMa - 07.99 csem P. Marchal Centre Suisse d'Electronique et de Microtechnique SA Jaquet-Droz 1 CH-2007 Neuchâtel

Bio-inspiration-1/PMa csem P. Marchal Centre Suisse d'Electronique et de Microtechnique SA Jaquet-Droz 1 CH-2007 Neuchâtel
Application-Specific Memory Interleaving Enables High Performance in FPGA-based Grid Computations Tom VanCourt Martin Herbordt {tvancour, bu.edu.

Application-Specific Memory Interleaving Enables High Performance in FPGA-based Grid Computations Tom VanCourt Martin Herbordt {tvancour, bu.edu.
CMOL overview ● CMOS / nanowire / MOLecular hybrids ● Uses combination of Micro – Nano – Nano implements regular blocks (ie memory) – CMOS used for logic,

CMOL overview ● CMOS / nanowire / MOLecular hybrids ● Uses combination of Micro – Nano – Nano implements regular blocks (ie memory) – CMOS used for logic,
Reconfigurable Computing S. Reda, Brown University Reconfigurable Computing (EN2911X, Fall07) Lecture 08: RC Principles: Software (1/4) Prof. Sherief Reda.

Reconfigurable Computing S. Reda, Brown University Reconfigurable Computing (EN2911X, Fall07) Lecture 08: RC Principles: Software (1/4) Prof. Sherief Reda.
State Machines Timing Computer Bus Computer Performance Instruction Set Architectures RISC / CISC Machines.

State Machines Timing Computer Bus Computer Performance Instruction Set Architectures RISC / CISC Machines.
Field Programmable Gate Array (FPGA) Layout An FPGA consists of a large array of Configurable Logic Blocks (CLBs) - typically 1,000 to 8,000 CLBs per chip.

Field Programmable Gate Array (FPGA) Layout An FPGA consists of a large array of Configurable Logic Blocks (CLBs) - typically 1,000 to 8,000 CLBs per chip.
Ontogenetic systems Drawing inspiration from growth and healing processes of living organisms… …and applying them to electronic computing systems Phylogeny.

Ontogenetic systems Drawing inspiration from growth and healing processes of living organisms… …and applying them to electronic computing systems Phylogeny.

Similar presentations

Ads by Google