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Structures for Discrete-Time Systems 主講人：虞台文
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Content Introduction Block Diagram Representation Signal Flow Graph Basic Structure for IIR Systems Transposed Forms Basic Structure for FIR Systems Lattice Structures
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Structures for Discrete-Time Systems Introduction
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Characterize an LTI System Impulse Response z-Transform Difference Equation
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Example Computable Noncomputable
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Basic Operations Computable Addition Multiplication Delay In fact, there are unlimited variety of computational structures.
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Why Implement Using Different Structures? Finite-precision number representation of a digital computer. Truncation or rounding error. Modeling methods: – Block Diagram – Signal Flow Graph
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Block Diagram Representation + x1(n)x1(n) x2(n)x2(n) x 1 (n) + x 2 (n) Adder x(n)x(n) a ax(n) Multiplier x(n)x(n) x(n1)x(n1) z1z1 Unit Delay
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Example x(n)x(n) + + b a1a1 z1z1 z1z1 a2a2 y(n)y(n) y(n1)y(n1) y(n2)y(n2)
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Higher-Order Difference Equations
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Block Diagram Representation (Direct Form I) + z1z1 z1z1 + z1z1 + b0b0 b1b1 bM1bM1 bMbM x(n)x(n) x(n1)x(n1) x(n2)x(n2) x(nM)x(nM) + z1z1 z1z1 + z1z1 + a1a1 aN1aN1 aNaN y(n)y(n) y(n1)y(n1) y(n2)y(n2) y(nM)y(nM) v(n)v(n)
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+ z1z1 z1z1 + z1z1 + b0b0 b1b1 bM1bM1 bMbM x(n)x(n) x(n1)x(n1) x(n2)x(n2) x(nM)x(nM) + z1z1 z1z1 + z1z1 + a1a1 aN1aN1 aNaN y(n)y(n) y(n1)y(n1) y(n2)y(n2) y(nM)y(nM) v(n)v(n)
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+ z1z1 z1z1 + z1z1 + b0b0 b1b1 bM1bM1 bMbM x(n)x(n) x(n1)x(n1) x(n2)x(n2) x(nM)x(nM) + z1z1 z1z1 + z1z1 + a1a1 aN1aN1 aNaN y(n)y(n) y(n1)y(n1) y(n2)y(n2) y(nM)y(nM) v(n)v(n)
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+ z1z1 z1z1 + z1z1 + b0b0 b1b1 bM1bM1 bMbM x(n)x(n) x(n1)x(n1) x(n2)x(n2) x(nM)x(nM) + z1z1 z1z1 + z1z1 + a1a1 aN1aN1 aNaN y(n)y(n) y(n1)y(n1) y(n2)y(n2) y(nM)y(nM) v(n)v(n) Implementing zeros Implementing poles
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Block Diagram Representation (Direct Form I) + z1z1 z1z1 + z1z1 + b0b0 b1b1 bM1bM1 bMbM x(n)x(n) x(n1)x(n1) x(n2)x(n2) x(nM)x(nM) + z1z1 z1z1 + z1z1 + a1a1 aN1aN1 aNaN y(n)y(n) y(n1)y(n1) y(n2)y(n2) y(nM)y(nM) v(n)v(n) How many Adders? How many multipliers? How many delays? How many Adders? How many multipliers? How many delays?
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Block Diagram Representation (Direct Form II) + z1z1 z1z1 + z1z1 + b0b0 b1b1 bN1bN1 bNbN x(n)x(n) + z1z1 z1z1 + z1z1 + a1a1 aN1aN1 aNaN y(n)y(n) w(n1)w(n1) w(n2)w(n2) w(nN)w(nN) w(n)w(n) Assume M = N
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Block Diagram Representation (Direct Form II) + z1z1 z1z1 + z1z1 + b0b0 b1b1 bN1bN1 bNbN x(n)x(n) + z1z1 z1z1 + z1z1 + a1a1 aN1aN1 aNaN y(n)y(n) w(n1)w(n1) w(n2)w(n2) w(nN)w(nN) w(n)w(n) Assume M = N
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Block Diagram Representation (Direct Form II) + z1z1 z1z1 + z1z1 + b0b0 b1b1 bN1bN1 bNbN x(n)x(n) + z1z1 z1z1 + z1z1 + a1a1 aN1aN1 aNaN y(n)y(n) w(n1)w(n1) w(n2)w(n2) w(nN)w(nN) w(n)w(n) Assume M = N Implementing zeros Implementing poles
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Block Diagram Representation (Direct Form II) + z1z1 z1z1 + z1z1 + b0b0 b1b1 bN1bN1 bNbN x(n)x(n) + z1z1 z1z1 + z1z1 + a1a1 aN1aN1 aNaN y(n)y(n) w(n1)w(n1) w(n2)w(n2) w(nN)w(nN) w(n)w(n) Assume M = N How many Adders? How many multipliers? How many delays? How many Adders? How many multipliers? How many delays?
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Block Diagram Representation (Canonic Direct Form) + + + b0b0 b1b1 bN1bN1 bNbN x(n)x(n) + z1z1 z1z1 + z1z1 + a1a1 aN1aN1 aNaN y(n)y(n) Assume M = N
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Block Diagram Representation (Canonic Direct Form) + + + b0b0 b1b1 bN1bN1 bNbN x(n)x(n) + z1z1 z1z1 + z1z1 + a1a1 aN1aN1 aNaN y(n)y(n) Assume M = N How many Adders? How many multipliers? How many delays? max(M, N) How many Adders? How many multipliers? How many delays? max(M, N)
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Structures for Discrete-Time Systems Signal Flow Graph
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Nodes And Branches wj(n)wj(n) wk(n)wk(n) Associated with each node is a variable or node value.
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Nodes And Branches wj(n)wj(n) wk(n)wk(n) Brach ( j, k ) Each branch has an input signal and an output signal. Input w j (n) Output: A linear transformation of input, such as constant gain and unit delay.
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More on Nodes wj(n)wj(n) wk(n)wk(n) An internal node serves as a summer, i.e., its value is the sum of outputs of all branches entering the node.
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Source Nodes Nodes without entering branches xj(n)xj(n)wk(n)wk(n) Source node j
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Sink Nodes Nodes that have only entering branches yk(n)yk(n)wj(n)wj(n) Sink node k
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Example x(n)x(n) y(n)y(n)w1(n)w1(n) w2(n)w2(n) a b c d e Source Node Sink Node
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Block Diagram vs. Signal Flow Graph x(n)x(n) + a z1z1 + b1b1 b0b0 w(n)w(n)y(n)y(n) x(n)x(n) w1(n)w1(n) w2(n)w2(n)w3(n)w3(n) a b1b1 b0b0 z1z1 1 2 3 4 w4(n)w4(n) y(n)y(n)
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x(n)x(n) + a z1z1 + b1b1 b0b0 w(n)w(n)y(n)y(n) x(n)x(n) w1(n)w1(n) w2(n)w2(n)w3(n)w3(n) a b1b1 b0b0 z1z1 1 2 3 4 w4(n)w4(n) y(n)y(n)
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Structures for Discrete-Time Systems Basic Structure for IIR Systems
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Criteria Reduce the number of constant multipliers – Increase speed Reduce the number of delays – Reduce the memory requirement Modularity: VLSI design The effects of finite register length and finite- precision arithmetic.
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Basic Structures Direct Forms Cascade Form Parallel Form
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Direct Forms
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Direct Form I b0b0 b1b1 x(n)x(n) x(n1)x(n1) x(n2)x(n2) x(nN)x(nN) y(n)y(n) b2b2 b N-1 bNbN x(n N+1) a1a1 a2a2 a N-1 aNaN y(n1)y(n1) y(n2)y(n2) y(nN)y(nN) y(n N+1) z1z1 z1z1 z1z1 z1z1 z1z1 z1z1 v(n)v(n)
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Direct Form I b0b0 b1b1 x(n)x(n) x(n1)x(n1) x(n2)x(n2) x(nN)x(nN) y(n)y(n) b2b2 b N-1 bNbN x(n N+1) a1a1 a2a2 a N-1 aNaN y(n1)y(n1) y(n2)y(n2) y(nN)y(nN) y(n N+1) z1z1 z1z1 z1z1 z1z1 z1z1 z1z1 v(n)v(n)
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Direct Form II x(n)x(n) y(n)y(n) w(n)w(n) b0b0 b1b1 b2b2 b N-1 bNbN a1a1 a2a2 a N-1 aNaN z1z1 z1z1 z1z1
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Direct Form II x(n)x(n) y(n)y(n) w(n)w(n) b0b0 b1b1 b2b2 b N-1 bNbN a1a1 a2a2 a N-1 aNaN z1z1 z1z1 z1z1
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Example x(n)x(n) y(n)y(n) z1z1 z1z1 z1z1 z1z1 0.75 0.125 2 x(n)x(n) y(n)y(n) z1z1 z1z1 0.75 0.125 2 Direct Form I Direct Form II
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Cascade Form
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2nd Order System 2nd Order System 2nd Order System 2nd Order System 2nd Order System 2nd Order System
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Cascade Form x(n)x(n)y(n)y(n) z1z1 z1z1 a 11 a 21 b 11 b 21 b 01 z1z1 z1z1 a 12 a 22 b 12 b 22 b 01 z1z1 z1z1 a 13 a 23 b 13 b 23 b 03
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Another Cascade Form
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Parallel Form
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Real Poles Complex Poles Poles at zero Group Real Poles
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Parallel Form z1z1 z1z1 a1ka1k a2ka2k e0ke0k e1ke1k
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x(n)x(n) y(n)y(n)
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Example 8 x(n)x(n)y(n)y(n) z1z1 z1z1 0.75 0.125 8 77
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Example z1z1 0.5 18 8 x(n)x(n)y(n)y(n) z1z1 0.25 25
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Structures for Discrete-Time Systems Transposed Forms
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Signal Flow Graph Transformation To transform signal graphs into different forms while leaving the overall system function between input and output unchanged.
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Transposition of Signal Flow Graph Reverse the directions of all arrows. Changes the roles of input and output. x(n)x(n)y(n)y(n) z1z1 a x(n)x(n)y(n)y(n) z1z1 a
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Transposition of Signal Flow Graph x(n)x(n)y(n)y(n) z1z1 a x(n)x(n)y(n)y(n) z1z1 a Are there any relations between the two systems?
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Example: z1z1 a x(n)x(n)y(n)y(n) z1z1 a x(n)x(n)y(n)y(n) z1z1 a x(n)x(n)y(n)y(n)
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Transposition of Signal Flow Graph Reverse the directions of all arrows. Changes the roles of input and output. x(n)x(n)y(n)y(n) z1z1 a x(n)x(n)y(n)y(n) z1z1 a Detail proof see reference
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Structures for Discrete-Time Systems Basic Structure for FIR Systems
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FIR For causal FIR systems, the system function has only zeros.
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Direct Form x(n)x(n) y(n)y(n) z1z1 z1z1 z1z1 h(0)h(1)h(2) h(M1)h(M1) h(M)h(M)
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x(n)x(n) y(n)y(n) z1z1 z1z1 z1z1 h(0)h(1)h(2) h(M1)h(M1) h(M)h(M) Direct Form x(n)x(n) y(n)y(n) z1z1 z1z1 z1z1 h(0)h(1)h(2) h(M1)h(M1) h(M)h(M)
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x(n)x(n) y(n)y(n) z1z1 z1z1 z1z1 h(0)h(1)h(2) h(M1)h(M1) h(M)h(M) Direct Form x(n)x(n) y(n)y(n) z1z1 z1z1 z1z1 h(0)h(1)h(2) h(M1)h(M1) h(M)h(M)
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Cascade Form
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x(n)x(n) y(n)y(n) z1z1 z1z1 b 01 b 11 b 21 z1z1 z1z1 b 02 b 12 b 22 z1z1 z1z1 b 1Ms b 2Ms b 0Ms
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M is evenM is odd h(M n) = h(n) h(M n) = h(n) Structures for Linear Phase Systems A generalized linear phase system satisfies: h(M n) = h(n) for n = 0,1,…,M h(M n) = h(n) for n = 0,1,…,M or Type I Type III Type II Type VI
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Type I
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x(n)x(n) y(n)y(n) z1z1 z1z1 z1z1 z1z1 z1z1 z1z1 h(M/2) h(M/2 1) h(0) h(1)h(2)
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Type II, III and VI Construct them in a similar manner by yourselves.
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Structures for Discrete-Time Systems Lattice Structures
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FIR Lattice Consider x(n)= (n), one will see
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FIR Lattice Consider x(n)= (n), one will see
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FIR Lattice Consider x(n)= (n), one will see
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FIR Lattice Define Consider x(n)= (n), one will see
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FIR Lattice Show that Define
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FIR Lattice i=1: Show that
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FIR Lattice i = n: Assumed true Show that i = n+1 also true. Prove
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FIR Lattice =
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m=0 1111111 k1k1 k2k2 k3k3 k4k4 k5k5 k6k6 m=1 m=2 m=3 m=4 m=5 m=6 Given the lattice, to find A(z).
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FIR Lattice Given A(z), to find the lattice. m=0 1111111 m=1 m=2 m=3 m=4 m=5 m=6
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m=0 1111111 m=1 m=2 m=3 m=4 m=5 m=6 FIR Lattice Given A(z), to find the lattice.
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Example 1 1 1 1 1 1 1 1 m=0 m=1 m=2 m=3 0.6728 0.7952 0.1820 0.9 0.64 0.576
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Example 0.576 0.1820 0.6728 1 1 1 1 1 1 1 1 m=0 m=1 m=2 m=3 0.6728 0.7952 0.1820 0.9 0.64 0.576
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Inverse Filter
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All-Pole Filter
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Example 0.6728 0.6728 0.1820 0.1820 0.576 0.576 0.1820 0.6728
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Example 0.6728 0.6728 0.1820 0.1820 0.576 0.576 0.9 0.64 0.576
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Stability of All-Pole Filter All zeros of A(z) have to lie within the unit circle. Necessary and sufficient conditions: All of k-parameters k i ’s satisfy |k i | < 1.
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Normalized Lattice
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Section i
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Normalized Lattice Section N Section N 1 Section 1 Section i
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Normalized Lattice Section i Three-Multiplier Form
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Normalized Lattice Four-Multiplier, Normalized Form Four-Multiplier, Kelly-Lochbaum Form Three-Multiplier Form
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Normalized Lattice Section N Section N 1 Section 1 Three-Multiplier Form
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Normalized Lattice Section N Section N 1 Section 1 Four-Multiplier, Normalized Form
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Normalized Lattice Section N Section N 1 Section 1 Four-Multiplier, Kelly-Lochbaum Form
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Lattice Systems with Poles and Zeros Section N 1 Section 1 Section N c0c0 c1c1 cN2cN2 cN1cN1 cNcN
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Lattice Systems with Poles and Zeros Section N 1 Section 1 Section N c0c0 c1c1 cN2cN2 cN1cN1 cNcN
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Lattice Systems with Poles and Zeros
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Example 0.6728 0.6728 0.1820 0.1820 0.576 0.576 c3c3 c2c2 c1c1 c0c0
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0.6728 0.6728 0.1820 0.1820 0.576 0.576 c3c3 c2c2 c1c1 c0c0 Example 1 1 1 1 1 1 1 1 m=0 m=1 m=2 m=3 0.6728 0.7952 0.1820 0.9 0.64 0.576
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0.6728 0.6728 0.1820 0.1820 0.576 0.576 13.95.46124.5404 Example
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