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Midterm Exam ReviewCopyright 2006 - Joanne DeGroat, ECE, OSU1 Midterm Exam Notes
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Midterm Exam ReviewCopyright 2006 - Joanne DeGroat, ECE, OSU2 Midterm Exam – ECE762 GENERAL Open book/open notes – suggestion: make up 2 pages of notes from the book and lecture slides (this is an excellent way to review) NO USE OF ANY OUTSIDE ELECTRONIC COMMUNICATION DURING THE EXAM. No Google searches during the exam. The electronic text book can be used. Online lecture slide can be used. Be sure you name is on your exam!!! EE Honor Code applies
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What is on the exam Look at website and topic of lectures Course Intro VHDL Introduction Data Paths 1 & 2 Language Overview I, II, and III Attributes Modeling of leaf units using a dataflow modeling style Know the difference in behavioral modeling, structural modeling, an ARCHITECTURE with only concurrent signal assignment statements in it, etc. Basic concepts of timing and signal updating. Midterm Exam ReviewCopyright 2006 - Joanne DeGroat, ECE, OSU3
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Modeling The dataflow style Concurrent signal assignment Selected signal assignment Conditional signal assignment Structural The component declaration Component configuration Component instantiation Midterm Exam ReviewCopyright 2006 - Joanne DeGroat, ECE, OSU4
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Timing simulation cycle/resolution Understand the simulation cycle and updating the projected output waveform Know what a driver is and its significance Know VHDL resolution Know the state machine design methodology Know the IEEE floating point standard How to convert from base 10 to floating point representation and how to convert back. Midterm Exam ReviewCopyright 2006 - Joanne DeGroat, ECE, OSU5
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Transactions Know the difference between transactions and events. Know the difference between signals and variables. Midterm Exam ReviewCopyright 2006 - Joanne DeGroat, ECE, OSU6
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Know datapath operation Concept of dual ported registers The difference between accumulator architectures and a general register configuration. Midterm Exam ReviewCopyright 2006 - Joanne DeGroat, ECE, OSU7
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