1. Advanced Digital Design Asynchronous Design: Principles by A. Steininger and M. Delvai Vienna University of Technology

2. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 2 Previous Conclusion The purpose of a design style is to provide information for flow control. The purpose of a design style is to provide information for flow control. Boolean Logic alone cannot provide this information. Boolean Logic alone cannot provide this information. Severe technological problems force us to question the current (synchronous) design practice. We shall focus on that. Severe technological problems force us to question the current (synchronous) design practice. We shall focus on that. Alternatives must be evaluated very critically with respect to improvements concerning power, area, robustness, ease of composition, testability and performance. Alternatives must be evaluated very critically with respect to improvements concerning power, area, robustness, ease of composition, testability and performance. recal l

3. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 3 What we actually need SRCSNK f(x) When it is valid and consistent When SNK has consumed the previous one When can SNK use its input? When can SRC apply the next input? recal l

4. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 4 Ideal Design Method An ideal design method … minimizes power consumption minimizes power consumption miminizes circuit overhead miminizes circuit overhead naturally supports composability naturally supports composability naturally aids testability naturally aids testability yields robust circuits yields robust circuits yields fast circuits. yields fast circuits. recal l

5. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 5 Outline The Handshake Principle The Handshake Principle Sutherland‘s Micropipeline Sutherland‘s Micropipeline Transition Signaling & Muller C-Element Transition Signaling & Muller C-Element The Bounded Delay Approach The Bounded Delay Approach Other Delay Models Other Delay Models Hazards: Identification & Remedies Hazards: Identification & Remedies Huffmann Circuits Huffmann Circuits Asynchronous State Machines Asynchronous State Machines

6. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 6 Our Options We must only use consistent input vectors We must only use consistent input vectors How can we tell an input vector is consistent? How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach / global time base synchronous approach / global time base asynchronous/bounded delay asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive asynchronous/delay insensitive recal l

7. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 7 „The control flow requires agreement between source and sink. For this purpose they need to communicate“ „The control flow requires agreement between source and sink. For this purpose they need to communicate“ Source indicates capture condition for sink. Source indicates capture condition for sink. Sink indicates issue condition for source. Sink indicates issue condition for source. Asynchronous Philosophy „HANDSHAKE“

8. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 8 Handshake Principle SRCSNK f(x) When it is valid and consistent When SNK has consumed the previous one When can SNK use its input? When can SRC apply the next input? REQ: „Data word valid, you can use it“ ACK: „Data word consumed, send the next“

9. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 9 f(x) R1R2 C C REQ n-1 ACK n+1 capture „bundled data“ (handshake performed for „bundle“ of data) Micropipeline: Principle REQ n ACK n

10. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 10 A very Important Detail The handshake establishes a closed-loop control for the data flow between sender and receiver The handshake establishes a closed-loop control for the data flow between sender and receiver This makes operation more robust than in the synchronous (= open-loop) case This makes operation more robust than in the synchronous (= open-loop) case The art of asynchronous design is to make many of these closed loops interoperate properly The art of asynchronous design is to make many of these closed loops interoperate properly This is much more complicated than a synchronous design. This is much more complicated than a synchronous design.

11. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 11 Micropipe: Capturing capture data if predecessor has new data available (REQ n-1 ) and predecessor has new data available (REQ n-1 ) and successor is ready to accept new data (ACK n+1 ) successor is ready to accept new data (ACK n+1 ) produce  at capture (output) after  of REQ and  of ACK produce  at capture (output) after  of REQ and  of ACK Muller C-Element C REQ n-1 ACK n+1

12. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 12 Muller C-Element RS reset set a b y IF a = = b THEN y = a ELSE hold y C ab y C a b y

13. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 13 Muller C-Element: Circuit [Sutherland] [Martin] [van Berkel]

14. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 14 „FIFO for transitions“ C C C R OUT A OUT R IN Elastic Pipeline

15. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 15 initial state C C C R OUT A OUT R IN Elastic Pipeline

16. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 16 request (rising edge) C C C R OUT A OUT R IN Elastic Pipeline

17. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 17 request passes stage 1 C C C R OUT A OUT R IN Elastic Pipeline

18. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 18 request passes stage 2 C C C R OUT A OUT R IN Elastic Pipeline

19. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 19 request passes stage 3 => output C C C R OUT A OUT R IN Elastic Pipeline

20. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 20 further request (falling edge) C C C R OUT A OUT R IN Elastic Pipeline

21. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 21 new request passes stage 1 C C C R OUT A OUT R IN Elastic Pipeline

22. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 22 new request passes stage 2 C C C R OUT A OUT R IN Elastic Pipeline

23. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 23 new request blocked for stage 3 C C C R OUT A OUT R IN Req 1 remains „stored“ Elastic Pipeline

24. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 24 one more request … C C C R OUT A OUT R IN Elastic Pipeline

25. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 25 … passes stage 1 only … C C C R OUT A OUT R IN Elastic Pipeline

26. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 26... ands remains stored there C C C R OUT A OUT R IN Req 1 stored here Req 2 stored here Req 3 stored here Elastic Pipeline

27. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 27 acknowledge from output (rising edge) C C C R OUT A OUT R IN Req 1 Req 2 Req 3 Elastic Pipeline

28. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 28 ack passes stage 3 C C C R OUT A OUT R IN Elastic Pipeline

29. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 29 stage 2 is now free for… C C C R OUT A OUT R IN Req 2 Req 3 Elastic Pipeline

30. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 30 … request from stage 1 C C C R OUT A OUT R IN Req 2 Req 3 Elastic Pipeline

31. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 31 new ack (falling edge) … C C C R OUT A OUT R IN Req 2 Req 3 Elastic Pipeline

32. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 32... allows remaining request to move up to stage 3 C C C R OUT A OUT R IN Req 3 Elastic Pipeline

33. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 33 ready for new req or ack C C C R OUT A OUT R IN Req 3 Elastic Pipeline

34. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 34 Micropipe: Implementation comb REQ ACK Capture/Pass Register

35. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 35 Capture/Pass Register must react to both edges („two phase handshake“) must react to both edges („two phase handshake“) has dedicated input for both, „capture“ and „pass“ has dedicated input for both, „capture“ and „pass“ has delayed output for both control inputs („capture done“, „pass done“) to make sure capture occurs before „capture done“ is output has delayed output for both control inputs („capture done“, „pass done“) to make sure capture occurs before „capture done“ is output c pp cc p

36. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 36 Transition Signaling Information conveyed by edges, not by state Advantage: edges also contain time information Advantage: edges also contain time information Drawback: need two rails per bit Drawback: need two rails per bit A0A0 A1A1 011 1 0

37. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 37 Terminology consistent DW: all bits belong to the same context valid signal: result of function applied to consistent DW recal l

38. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 38 A0A0 A1A1 B0B0 B1B1 Y = A or B A=0 A=1 B=1 B=0 Y0Y0 Y1Y1 Y=1 A Trans. Signaling - Example

39. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 39 Closed loop vs. open loop Previous example assumed a certain procedure: (1)one input changes (once!) (2)other input changes (once!) (3)then output changes (once!) Is this realistic? NO, if inputs are not correlated with output („open loop operation“) NO, if inputs are not correlated with output („open loop operation“) YES, in case of synchronization by means of handshake, i.e. in Micropipeline („closed loop operation“) YES, in case of synchronization by means of handshake, i.e. in Micropipeline („closed loop operation“)

40. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 40 2 Phase vs. 4 Phase 2 phase protocol: 2 phase protocol: 4 phase protocol 4 phase protocol REQ ACK REQ ACK REQ ACK

41. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 41 Micropipe: Implementation comb DELAY ELEMENT

42. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 42 The need for a delay SRCSNK f(x) REQ: „Data word valid, you can use it“ ACK: „Data word consumed, send the next“ event = latching of data word safe (?) event = issue of data word! race condition !

43. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 43 [Centronix Spec for ETRAX100LX, „Fastbyte Mode“] Data „REQ“ „ACK“ Example: Centronix

44. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 44 Criticality of ACK cannot measure „act of latching“ as an event cannot measure „act of latching“ as an event use latching command instead use latching command instead fork produces race between trigger process and next data wave fork produces race between trigger process and next data wave race is uncritical (but still exists!) race is uncritical (but still exists!) SRCSNK f(x) FF2 „latch!“

45. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 45 Criticality of REQ SRCSNK f(x) cannot use issue trigger as an event: cannot use issue trigger as an event: produces unacceptable race between data and REQ produces unacceptable race between data and REQ must introduce timer (bounded delay) must introduce timer (bounded delay) OR: find better event (downstream) OR: find better event (downstream) completion detection

46. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 46 coordinate SNK & SRC by a handshake coordinate SNK & SRC by a handshake This works (quite) well for „ACK“, but This works (quite) well for „ACK“, but still requires a timer-solution for REQ still requires a timer-solution for REQ So what have we actually gained? Bounded Delay approach Timer SRC TRG SNK (REQ) TRG SRC (ACK) Timer SNK  SNK  SRC

47. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 47 synchronous model known bounds for delays, global timing known bounds for delays, global timing bounded delay model (fundamental) bounded delay model (fundamental) known bounds for absolute delays, local timing known bounds for absolute delays, local timing scalable-delay-insensitive model scalable-delay-insensitive model bounds for relative deviation between delays known bounds for relative deviation between delays known quasi-delay-insensitive quasi-delay-insensitive output paths of a fork have same delay output paths of a fork have same delay delay insensitive delay insensitive no restrictions on delays (just finite) no restrictions on delays (just finite) Softening the restrictions

48. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 48 The Issue Condition Control TRGSRC: Have SRC issue the next data word such that the current one can still be safely consumed by SNK. Formal Condition: t invalid,x > t safe,x  src > -  invalid recal l  SNK

49. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 49 Bundled Data: Issue Cond. Delay source trigger by Delay source trigger by  snk =  snktrg +  cons +  src This is the delay between „capture“ and „capture done“ in the micropipeline. This is the delay between „capture“ and „capture done“ in the micropipeline. For  snk = 0 we end up like in the synchronous case: For  snk = 0 we end up like in the synchronous case:  src = -( snktrg +  cons ) this is not safe, but works

50. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 50 The Capture Condition Control TRGSNK: Have SNK capture data only after it has become consistent. Formal Condition: t cons,x > t snkrdy,x  snk > -  snktrg recal l  SRC

51. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 51 Bundled Data: Capture Cond. Delay source trigger by Delay source trigger by  src =  src +  proc +  snk +  snk This definitely requires a delay element. This definitely requires a delay element. like in the synchronous case we end up estimating the involved delays like in the synchronous case we end up estimating the involved delays

52. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 52 the skew problem still exists (!) the skew problem still exists (!) need to determine suitable value for  need to determine suitable value for  need to make worst case assumptions for determination of  need to make worst case assumptions for determination of  does not work without constraints on the individual path delays does not work without constraints on the individual path delays „Bounded Delay Model“ Drawback of the delay

53. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 53 What we actually need SRCSNK f(x) When it is valid and consistent When can SNK use its input? recal l „completion detection“: When are computation & transmission complete and data actually stable?

54. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 54 Current Sensing: Idea Transitions on data rails cause dynamic current Transitions on data rails cause dynamic current In the absence of dynamic current data must be stable In the absence of dynamic current data must be stable current sensor can be used for completion detection current sensor can be used for completion detection

55. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 55 Current Sensing: Problems inversion of causality is not safe: inversion of causality is not safe: What if bit changes after circuit has been considered stable? leakage dominates – proportion of dynamic current is decreasing leakage dominates – proportion of dynamic current is decreasing current sensor is undesired analog circuitry current sensor is undesired analog circuitry

56. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 56 need to determine clock period need to determine clock period circuit functionality is technology dependent circuit functionality is technology dependent considerable design efforts, large design loops considerable design efforts, large design loops need to make worst-case assumptions need to make worst-case assumptions necessarily pessimistic necessarily pessimistic no robustness wrt. exceeding them no robustness wrt. exceeding them need to maintain global synchrony need to maintain global synchrony clock distribution problems clock distribution problems power consumption problems power consumption problems Gain of Bounded Delay timer settings

57. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 57 Huffman Circuits „glitch free“ logic circuits „glitch free“ logic circuits add redundant P-terms to minimized representation add redundant P-terms to minimized representation problems: problems: not all glitches can be avoided not all glitches can be avoided severe restrictions for inputs severe restrictions for inputs redundant terms not testable redundant terms not testable

58. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 58 Input Restrictions Fundamental Mode („Grey-Coding“) Fundamental Mode („Grey-Coding“) only one input-bit changes at a time only one input-bit changes at a time  delay in feedbacks required  difficult state coding  not suitable for data path elements Burst Mode Burst Mode groups of inputs may change groups of inputs may change  requires local clock  requires local clock

59. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 59 Delay Elements Combinational logic Outputs Next State Current State Inputs Z1Z1 ZmZm x1x1 xnxn y1y1 ykyk Delayed Feedback

60. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 60 feedback delay feedback delay implies timing-assumptions („Bounded Delay“) implies timing-assumptions („Bounded Delay“) considerably slows down operation considerably slows down operation complicated design complicated design state coding, data path state coding, data path localen clock for burst mode localen clock for burst mode testing of redundant terms cumbersome testing of redundant terms cumbersome no structuring no structuring not suitable as a stand-alone solution A Huffman Circuits: Problems

61. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 61 Asynchronous FSM transition between states triggered by input edge rather than by synchronous clock transition between states triggered by input edge rather than by synchronous clock essential hazard: input transition might be perceived after resulting state change at some point => glitch or wrong next state essential hazard: input transition might be perceived after resulting state change at some point => glitch or wrong next state need delay to separate transitions in feedback from (primary) input transitions need delay to separate transitions in feedback from (primary) input transitions restrictions for inputs and feedback apply restrictions for inputs and feedback apply

62. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 62 FSM versus AFSM f(x ) Mealy Reg clk input output 

63. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 63 State Diagram AFSM s0 s1 s2 s3 10/10 00/11 01/10 00/00 ab/xy s0 s1 s2 s3 a+/x+ a-/y+ b+/y- b-/x- ab/xy Burst Mode Diagram [Chris Myers, Asynchronous Circuit Design. Wiley 2001]

64. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 64 Huffmann Flow Table 00011110 s0s0,00––s1,10 s1s2,11––s1,10 s2s2,11s3,10–– s3s0,00s3,10–– a,b input output next state state stable [Chris Myers, Asynchronous Circuit Design. Wiley 2001]

65. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 65 Conclusion Alternatively to a global time base a handshake can establish the required synchronization between source and sink: The source issues a REQ to signal that new data are valid, and the sink issues ACK when it is ready for the next data. Alternatively to a global time base a handshake can establish the required synchronization between source and sink: The source issues a REQ to signal that new data are valid, and the sink issues ACK when it is ready for the next data. In principle the handshake can establish a closed control loop for data flow, which yields higher robustness but variable timing. In principle the handshake can establish a closed control loop for data flow, which yields higher robustness but variable timing. The micropipeline is the basic approach for structuring asynchronous circuits. It couüples individual source/sink pairs The micropipeline is the basic approach for structuring asynchronous circuits. It couüples individual source/sink pairs

66. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 66 Conclusion The bundled data approach utilizes coupled timers for the control of REQ and ACK. This saves the need for a clock tree, but does not solve the conceptual problem of coupling validity to time. The bundled data approach utilizes coupled timers for the control of REQ and ACK. This saves the need for a clock tree, but does not solve the conceptual problem of coupling validity to time. Huffman circuits are useful for designing small sub-circuits and state machines in a glitch-free manner. They do, however not provide a generally applicable design solution. Huffman circuits are useful for designing small sub-circuits and state machines in a glitch-free manner. They do, however not provide a generally applicable design solution.