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COMPUTER ORGANIZATION LECTURE 3: ISA YASSER MOHAMMAD.

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Presentation on theme: "COMPUTER ORGANIZATION LECTURE 3: ISA YASSER MOHAMMAD."— Presentation transcript:

1 COMPUTER ORGANIZATION LECTURE 3: ISA YASSER MOHAMMAD

2 WHAT IS ISA?  ISA (Instruction Set Architecture)  Instructions are the basic actions that the processor can understand  ADD a,b,c  ISA = instructions + programmer visible hardware  Design Principles (RISC vs. CISC):  Make it simple  Make it fast

3 FROM C TO ASSEMBLY

4 MIPS REGISTERS AND MEMORY

5 DEALING WITH MEMORY

6 MATH AND LOGIC Register vs. Immediate sources Where is not? Is sub necessary? Sll = shift left logical  is there is shift left ‘something-else’?

7 PROGRAM CONTROL

8 C TO ASSEMBLY (SLIGHTLY MORE COMPLEX) d[4] = d[2] + a; Assembly: # addi instructions as before lw $t0, 8($s4) # d[2] is brought into $t0 lw $t1, 0($s1) # a is brought into $t1 add $t0, $t0, $t1 # the sum is in $t0 sw $t0, 16($s4) # $t0 is stored into d[3]

9 NUMERIC REPRESENTATION  Review  Numbering systems (specially decimal, binary, and octal)  Conversion between numbering systems  Arithmetic in binary  Representation of signed numbers  Sign-magnitude  2’s complement You studied this like a 100 times before

10 QUIZZ  Represent the following numbers in 8 bit registers using 2’s complement  33  -25  0  127  -128

11 INSTRUCTION REPRESENTATION R format 1 instruction 1 word

12 ALL MIPS REPRESENTATIONS R I J

13 PROGRAM CONTROL s3 s4 s0 s1 s2

14 LOOP s6 s3 s5

15 INSTRUCTION EXECUTION (SIMPLIFIED)  Fetch  Decode  Execute Processor PC Memory Address Bus MAR MDR MCR Data Bus Control Bus ALU GPR Incrementer

16 PROGRAM CONTROL Instruction fetch, decode and execute stages What is PC?

17 EXAMPLE: BOUNDS CHECK SHORTCUT

18 PROCEDURES  Supporting procedures in Hw requires two conventions  How to call a function including how to pass parameters  How to return results and return execution

19 STEPS FOR PROCEDURE CALL

20 HOW IS IT DONE IN MIPS  Caller responsibilities (partial)  First four parameters in $a registers (4 of them)  The rest of the parameters in the stack  Execute: jal functionAddress  Callee responsibilities (partial)  Return value in $v0 registers (2 of them)  Execute: jr $ra

21 SIMPLE EXAMPLE Leaf_example: add $t0,$a0,$a1 # register $t0 contains g + h add $t1,$a2,$a3 # register $t1 contains i + j sub $v0,$t0,$t1 # f = $t0 – $t1, which is (g + h)–(i + j) # returns f jr ra X=leaf_example(4,5,6,7); addi $a0,$zero,4 addi $a1,$zero,5 addi $a2,$zero,6 addi $a3,$zero,7 jal Leaf_example add $s0,$zero,$v0 $s0

22 MORE THAN 4 PARAMETERS

23 SAVING CONVENTIONS  Caller saved:  Temp registers $t0-$t9  $ra (it’s about to get over-written),  $a0-$a3 (so you can put in new arguments)  Callee saved:  $s0-$s7 (these typically contain “valuable” data)

24 RECURSION EXAMPLE (FACTORIAL) fact: addi $sp, $sp, –8 # adjust stack for 2 items sw $ra, 4($sp) # save the return address sw $a0, 0($sp) # save the argument n slti $t0,$a0,1 # test for n < 1 beq $t0,$zero,L1 # if n >= 1, go to L1 addi $v0,$zero,1 # return 1 addi $sp,$sp,8 # pop 2 items off stack jr $ra # return to caller L1: addi $a0,$a0,–1 # n >= 1: argument gets (n – 1) jal fact # call fact with (n –1) lw $a0, 0($sp) # return from jal: restore argument n lw $ra, 4($sp) # restore the return address addi $sp, $sp, 8 # adjust stack pointer to pop 2 items mul $v0,$a0,$v0 # return n * fact (n – 1) jr $ra # return to the caller

25 MEMORY STRUCTURE

26 LOCAL VARIABLES

27 LARGE CONSTANTS

28 PC RELATIVE ADDRESSING VS. GLOBAL ADDRESSING  Branch is local and jump is global  Why?

29 BRANCHING FAR AWAY

30 JMP (26 AND 32 BITS

31 ADDRESSING MODES

32 ATOMIC LOAD AND STORE

33 ASSEMBLING


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