1. CIS 6930 Powerline Communications Special Issues (c) 2013 Richard Newman

2. Special Issues in PLC Noise PCS/VCS Hidden nodes High speed issues Cross-layer design Coexistence

3. Noise Low transmit power Statutory limits on emissions in varous bands Vary by country – FCC part 15 rules in US Lower in Europe, Japan, Korea High interference Dynamic and frequency-specific noise Impulse noise

4. Carrier Sense Desirable to avoid collisions Carrier sense (determine if medium is busy) Physical Carrier Sense (PCS) Possible in media with good SNR, strong carrier Not feasible in PLC, wireless Virtual Carrier Sense (VCS) Needed when PCS not possible Detect synch/delimiters Increases logic, complexity, time

5. Virtual Carrier Sense Needed when PCS not possible Carrier(s) difficult to detect directly (SNR) Detect synch/delimiters Circuit matches synch pattern when searching Looks for delimiter following synch Have to verify delimiter (false synch problem) Must listen for sufficient time to detect busy state Delimiters indicate busy duration Include type and length field if not fixed length Delimiter must be very robust, else collisions

6. Hidden Nodes Each node pair has channel characteristics Local noise Multipath effects Interference Attenuation Hidden nodes A may hear B but not C, B may hear A and C, etc. May be multiple layers Capture effect If A and C both send, B may receive one and not other Other sender acts as noise source, affects reliability

7. Hidden Node “Solutions” Request to send/Clear to sent (RTS/CTS) Source issues RTS Destination issues CTS if OK Handles one layer of hidden nodes Scheduling Coordinator issues TDM periods for node sets Reuse possible (disjoint node set neighborhoods) Challenging Multiple layers Tree topology helps (two-coloring problem)

8. High Speed Issues Many fixed overheads Synch, robust delimiters (SOF, ACK) Required idle time gaps (spaces) on wire RTS/CTS if hidden nodes Diminishing returns on PHY speed Time T = T fixed + T payload Efficiency E = T payload /(T fixed + T payload ) Must increase T payload to improve E T payload = Length/Data Rate = L payload /R payload Must increase payload length….

9. Cross-layer Design Noise at PHY level affects what MAC must do VCS requires robust delimiters Impulse noise affects error handling in MAC Speed of PHY affects MAC design Robust delimiters take long time Diminishing returns on PHY speed due to OH MAC results affect PHY Delimiter verification VCS derived from MAC processing

10. Coexistence In-home and access broadband PLC operate in same band Disaster if PLC technologies sabotage each other Standardization efforts CENELEC IEEE p1901 OPERA