1. PNPI / University of Florida Checking PC Timing Lev Uvarov CSC Time Synchronization Meeting May 12, 2009

2. PNPI / University of Florida Synchronization Meeting – May 12, 2009. Lev Uvarov 2 Trigger Timing Model for a TTC Command TTCci LHC Clock & Orbit CCBMPC CCB SP CORE AF Fiber 1 Fiber 3 SP CORE AF Fiber 180 Fiber 177 T = CONST MS T = (TTC=>CCB) + TTCrx + (MPC=>SP) + SPAF On a TTC_Resync command SPs equalize all 180 timing path latencies by adjusting the Alignment FIFO (AF) word count. TTC_BC0 takes the same path, except for going through TMB or (TMB => ALCT => TMB) If (TMB => ALCT => TMB) == Const then all BC0 path latencies also remain equal Brown – fiber delay; fixed, but presumably not equal Blue – adjustable latency SP CSR_AFD TTCci CCBMPC TMB

3. PNPI / University of Florida Synchronization Meeting – May 12, 2009. Lev Uvarov 3 Hardware test We can check that model works fine

4. PNPI / University of Florida Synchronization Meeting – May 12, 2009. Lev Uvarov 4 MPC Setup Set MPC in Transparent mode with CSR4 Load Link X <= Nx Where N = (TMB #) × 2 + (LCT #) - 1 TMB # = 1,…,9 LCT # = 0,1 Pick TMB #1, LCT #0 as a reference for Link 1 Pick others in turn for Link 2 & 3 1514131211109876543210 Link 3 <= N3Link 2 <= N2Link 1 <= N11

5. PNPI / University of Florida Synchronization Meeting – May 12, 2009. Lev Uvarov 5 SP Setup Configure CSR_DFC/MA/DD/W/0x81F1: DDM = 1 => VME readout mode FxA = 1 => readout only Front FPGAs, x = 1, …, 5 ZS = 0 => no zero suppression TB = 1 => readout 1 time bin only Issue TTC Resynch Configure CSR_FCC/MA/VM/W/0x0100 Issue L1A with ACT_FCC/MA/VM/W/0x8000 Read out DAT_DF/MA/DD/R 1514131211109876543210 DDMSPADTAF5AF4AF3AF2AF1AZSTB2TB1TB0 8 1F1

6. PNPI / University of Florida Synchronization Meeting – May 12, 2009. Lev Uvarov 6 ME Data The MEx Data word is present in the ME Data Block, if two conditions are met: The corresponding FnA bit is set to 1 (ACTIVE) and Either (ZS==0), or (ZS==1 AND VPx==1). The muon order always goes from ME1a to ME4c.