1. Chapter 4 From: Dr. Iyad F. Jafar Basic MIPS Architecture: Single-Cycle Datapath and Control

2. Outline Single-cycle Datapath Single-cycle Control Performance Analysis 2

3. Single-Cycle Datapath 3 The CPU’s datapath deals with moving data around The CPU’s control manages the data The first implementation considered All instructions start and finish execution in one cycle! This include the time required to fetch, decode, and execute the instruction In the following, we will consider the datapath of each of these steps

4. Single-Cycle Datapath 4 Fetch Datapath Fetching the instruction from memory requires Sending the PC to memory to read the instruction Update the PC to point to the next instruction Do we need an explicit write signal for writing the PC? Do we need an explicit read signal for reading the memory? PC Read Address Data Instruction Memory + 4 Instruction

5. Single-Cycle Datapath 5 Decode Datapath Regardless of the instruction Send the opcode (31-26) and the function (5-0) fields of the instruction to the control unit Read two registers; rs (25-21) and rt (20-16) Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 Control Unit R[rs] R[rt]

6. Single-Cycle Datapath 6 Inside the Register File How can we read a register out of 32 registers? Register 0 Register 1 Register 2 …. Register 31 32-to-1 MUX Read Register 1 Read Register 2 Read Data 1 Read Data 2 0 1 31 0 1

7. Single-Cycle Datapath 7 Inside the Register File Register Number 5-to-32 Decoder Write Data Register 0 D C Register 1 D C Register 2 D C ….. D C Register 31 D C Write 31 1 0 Clock

8. Single-Cycle Datapath 8 Execution Datapath R-type instructions (ADD, SUB, SLT, AND, OR) The two registers are read already! Perform operation based on OPCODE and FUNC fields Store the result back into the register file (the destination register is specified in rd field of the instruction (15-11) ! The register file is not written on every cycle! Need an explicit write signal Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 R[rs] R[rt] Instruction Write ALU RegWrite ALU Control

9. Single-Cycle Datapath 9 Execution Datapath Load Instruction Compute the load address Store the loaded data in the register file. The destination register is the rt field of the instruction (20-16) Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 R[rs] R[rt] Instruction Write ALU RegWrite ALU Control Address Data Data Memory Sign Ext. Write Data MemRead MemWrite

10. Single-Cycle Datapath 10 Execution Datapath Store Instruction Compute the load address Store register in the memory Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 R[rs] R[rt] Instruction Write ALU RegWrite ALU Control Address Data Data Memory Sign Ext. Write Data MemRead MemWrite

11. Single-Cycle Datapath 11 Execution Datapath Branch Instruction Compare the two registers Compute the branch address Change PC if true ! Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 Instruction Write RegWrite Sign Ext. ALU ALU Control PC + 4 x4 + Zero Branch Address 1 0 Zero

12. Single-Cycle Datapath 12 Execution Datapath Jump Instruction Compute the jump address Store it in the PC PC Read Address Data Instruction Memory + 4 Instruction x4 jump address 1 0 Jump

13. Single-Cycle Datapath 13 Creating the Single Datapath Assemble the datapath segments and add control lines and multiplexors as needed Single cycle design Fetch, decode and execute each instructions in one clock cycle No datapath resource can be used more than once per instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders) Multiplexors needed at the input of shared elements with control lines to do the selection Write signals to control writing to the Register File and Data Memory Cycle time is determined by length of the longest path

14. Instruction Format 14

15. Single-Cycle Datapath 15 Read Address Instr[31-0] Instruction Memory + PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 + PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch 0 1 Shift left 2 Instr[25-0] PC[31-28] Jump

16. Single-Cycle Control 16 Need to design the control that generates the appropriate control signals based on the Opcode and Function fields to Specify the operation of the ALU Control the data flow by selecting the appropriate input of the multiplexors With the following observations across different instructions Op field is always in bits 31-26 of the instruction Address of registers to be read are always specified by The rs field (bits 25-21) The rt field (bits 20-16) For LW and SW, the rs field is the base register Address of register to be written is in one of two places For LW, the address is the rt field (bits 20-16 ) For R-type, the address is the rd field (bits 15-11) Offset for BEQ, LW, and SW is always in bits 15-0 of the instruction

17. Single-Cycle Control 17 Signal NameEffect when Deassereted (0)Effect when Asserted (1) RegDst The destination register is from rt field The destination register is from rd field RegWriteNone Enable writing to the register selected by the Write register port ALUSrc The second ALU operand comes from the second register file output The second ALU operand is the sign extended offset PCSrcPC value is PC+4PC is the branch address MemReadNone Contents of memory address are put on Read data output MemWriteNone Data on the Write data input is placed in the specified address MemtoReg The data fed to the register file Write data input comes from ALU The data fed to the register file Write data input comes from memory ALUOp Used with the function field of the instruction to generate the ALUOp signal that specify the ALU operation

18. R-type Instruction Data/Control Flow 18 Read Address Instr[31-0] Instruction Memory + PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 + PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch 0 1 Shift left 2 Instr[26-0] PC[31-28] Jump

19. Load Word Instruction Data/Control Flow 19 Read Address Instr[31-0] Instruction Memory + PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 + PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch 0 1 Shift left 2 Instr[26-0] PC[31-28] Jump

20. Branch Equal Instruction Data/Control Flow 20 Read Address Instr[31-0] Instruction Memory + PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 + PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch 0 1 Shift left 2 Instr[26-0] PC[31-28] Jump

21. Jump Instruction Data/Control Flow 21 Read Address Instr[31-0] Instruction Memory + PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 + PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch 0 1 Shift left 2 Instr[26-0] PC[31-28] Jump

22. Single-Cycle Control 22 The Main Control Unit The input is the Op field (6 bits) from the instruction The output is nine control signals The truth table ! InputsOutputs Op5Op4Op3Op2Op1Op0 RegDist ALUsrc MemtoReg RegWrite MemRead MemWrite Branch ALUop1ALUop0 R-type000000100100010 LW100011011110000 SW101011X1X001000 BEQ000100X0X000101

23. Single-Cycle Control 23 The Main Control Unit To design the logic circuit, generate the appropriate minterms for each output signal Simply, use a PLA!

24. Single-Cycle Control 24 The ALU Control Unit It has two inputs ALUop (2 bits) from Main control Func (6 bits) from the instruction It has two outputs Bengate (1 bits) Operation (2 bits) Supported Operations FunctionBnegateOperation and000 or001 add010 sub110 slt111 ALU control ALUop Func Bnegate Operation

25. Single-Cycle Control 25 The ALU Control Unit Truth Table ! InputsOutputs ALUop1ALUop0 F5F4F3F2F1F0 Bnegate Operation 1 Operation 0 AND10100100000 OR10100101001 ADD10100000010 SUB10100010110 SLT10101010111 LW00n/a010 SW00n/a010 BEQ01n/a110

26. Single-Cycle Control 26 The ALU Control Unit Hardware Implementation Generating minterms!! Minimization!!

27. Performance Analysis 27 All instructions have to finish in one cycle! How long is the cycle time? Different units are used in different instructions Each unit has its own delay Need to find the longest path! Assume the following times Thus, the cycle time should be at least 8 ns R-type: Instr. FetchRegister ReadALU Register Write 6ns 8ns 7ns 5ns 2ns Branch: Instr. FetchRegister ReadALU LW: Instr. FetchRegister ReadALU Memory ReadRegister Write SW: Instr. FetchRegister ReadALU Memory Write Jump: Instr. Fetch UnitDelay ALU2 ns Memory2 ns Register File1 ns

28. Performance Analysis 28 The cycle time is fixed! However, not all instructions require the same time! There is a wasted time for some instructions?! Clock LWSW Cycle 1 Cycle 2 waste

29. Single Cycle Disadvantages & Advantages 29 Single-cycle implementation assumes that all instructions can execute in one cycles Advantages Simple and easy to understand Disadvantages Hardware duplication! Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instruction ( especially problematic for more complex instructions like floating point multiply)