1. Implementing Fast Image Processing Pipelines in a Codesign Environment Accelerate image processing tasks through efficient use of FPGAs. Combine already designed components at runtime to implement series of transformations Heather Quinn, Dr. Miriam LeeserDr. Laurie Smith King Northeastern UniversityCollege of the Holy Cross Start AppHW InitSend Data MedianRepgmEdge DetGet DataDisplay 300 ms.00105 ms per pixel.00105 ms per pixel 70 ms Median Filter & Edge Detection

2. Possible Implementations Inputs: a profiled library of image processing components, a pipeline, and an image Output: an assignment of each component to a hardware or software implementation

3. Median Filter  Edge Detection Profiles The fastest implementation changes with image size If only one component in hardware, choose Edge Detector Different algorithms used at runtime to determine best implementation. See poster for details.