1. Programmable Logic Devices

2. Principle of Operation: Example: X = A.B + A’.B’ requires that fuses f1 and f4 to be “blown”.

3. Programmable Logic Array (PLA)

4. Programmable Array Logic (PAL) Programmable AND & Fixed OR matrix Example:

5. PAL with Output Pin Folding Output enable Folded output Output Folding allows SOPs with number of minterms is larger than the number of single OR gate inputs Boolean feedback i.e. latches

6. Working with PALs Original PALs were One Time Programmable (OTP) devices GAL denotes a PAL that is user reprogrammable Examples: GAL 16L8 has 16 inputs/8 outputs GAL 16R8 contains an additional Data Register to implement sequential circuit GAL 16VR8 contains Output Logic Macrocell (OMCL) that allows it to be configured to either simple (boolean) mode or complex (sequential) mode.

8. Complex Programmable Logic Devices (CPLD) More recent PLDs increase the number of gates by several factors of magnitude allowing to implement a moderately complex digital systems. Combine thousands of Gates & Flip Flops Field Programmable Gate Arrays (FPGA) Latest devices allowing to implement entire fairly complex digital System On a Chip (SOC). Combine millions of Gates & FFs + SRAM Arrow of Time