1. 1 Lecture 4 PC structure and expansion cards Lecturer: Lyulicheva I.А.

2. 2 Content PC structure – buses and expansion cards DMA system System memory Historical overview of Intel MP

3. 3 System busses The PCI bus was introduced in 1991 as replacement for ISA. Intel launched their PCI bus chipsets along with the P5-based Pentium CPUs in 1993. Firm DEC and Apple also utilize the bus PCI in their computers. The standard (now at version 3.0) is found on PC motherboards to this day. The PCI standard supports Bridging. Cardbus, using the PCMCIA connector, is a PCI format that attaches peripherals to the Host PCI Bus via PCI to PCI Bridge. S tandard PCI. Strictly saying PCI bus is not local, because it has between itself and the local bus of processor the special bridge. Thus the standard PCI foresees the use of controller which carries out an arbitration on the bus PCI, and also accelerator. It does a bus independent of processor.

4. 4 System busses By basic principle for the bus PCI, there is application of the so-called bridges which carry out connection between the bus PCI and other busses. During passing of information a device which supports Bus Mastering takes a bus as a master- device. It release the CPU from operations of sending of commands and/or of information between two devices on one bus. The special case of Bus Mastering is the mode of DMA, which carries out-of-process sending of information only; controller DMA is engaged in this process in classic architecture of PC.

5. PCI-lines (32-bit PCI connector pinout) Contains

6. PCI-lines (PCI connector pinout) Contains AD0-31 lines (so AB and DB are multiplexed!!) And some Control Bus signals combined with LIS and cards signals. Control signals are: CLK, GND, IOPWR (+5 or +3.3 М), RST, LOCK#, ACK64#REQ64#... Interrupt controllers signals are: INTA#, INTB#,INTC,#INTD# Etc. Self work if you wish.

7. 7 System memory and DMA Direct access to memory (DMA) is a method of direct address to memory, without the using of processor. DMA are useful for the exchange of large data arrays between system memory and I\O devices.

8. 8 DMA System Every Bus has a Mastering-device, that allows to be delivered problems with distributing of DMA- channels and to overcome limitation of standard DMA-comptroller (16-rozryadnist', to adress ability only the first 16 Mb of OZU, low fast-acting and others like that). Concerning built on IDE (for example, HD, CD- ROM) Bus Mastering IDE means the presence of certain charts on a system board, which allow to carry out communication of data from a hard disk in the round of CPU.

9. 9 System busses. АGP AGP Bus Bacause one bus of PC PCI was not enough for sending of graphic and videodata inside of graphic subsystem an additional bus was needed. Intel introduced the AGP bus in 1997 as a dedicated video acceleration solution. AGP devices are logically attached to the PCI bus over a PCI-to-PCI bridge. Though termed a bus, AGP usually supports only a single card at a time AGP (if it is present) make a channel transmissions between video adapters and RAM. Nowadays when PCI-Express bus exists AGP is on no use.

11. System busses. PCI-express From 2005 PCI-Express has been replacing both PCI and AGP. This standard, approved in 2004, implements the logical PCI protocol over a serial communication interface. Officially abbreviated as PCIe it is a high-speed serial computer expansion bus standard designed to replace the older PCI, PCI-X, and AGP bus standards.

12. System busses. PCI-express In virtually all modern (as of 2012) PCs, from consumer laptops and desktops to enterprise data servers, the PCIe bus serves as the primary motherboard-level interconnect, connecting the host system-processor with both integrated- peripherals (surface-mounted LICs) and add-on peripherals (expansion cards.) In most of these systems, the PCIe bus co-exists with one or more legacy PCI buses, for backward compatibility with the large body of PCI peripherals.

13. System busses. PCI-express Interconnect PCIe devices communicate via a logical connection called an interconnect or link. A link is a point-to-point communication channel between two PCIe ports, allowing both to send/receive ordinary PCI-requests (configuration read/write, I/O read/write, memory read/write) and interrupts (INTx). At the physical level, a link is composed of 1 or more lanes. Low-speed peripherals (such as an 802.11 Wi-Fi card) use a single-line (×1) link, while a graphics adapter typically uses a much wider (and thus, faster) 16-line link.

14. Memory of modern MPS Inside (MB) memory CPU registers (later) L1 cash L2 cash… etc. System memory Outside memory: HDD CD/DVD Flash-memory FDD и др. Memory hierarhy in modern PC is very wide and it serves to increase of the productivity of MP systems.

15. System memory classification The three main forms of modern RAM are static RAM (SRAM), dynamic RAM (DRAM) and Phase-change memory (PRAM). In SRAM, a bit of data is stored using the state of a flip-flop. This form of RAM is more expensive to produce, but is generally faster and requires less power than DRAM. DRAM stores a bit of data using a transistor and capacitor pair, which together comprise a memory cell. The capacitor holds a high or low charge (1 or 0), and the transistor acts as a switch that lets the control circuitry on the chip read the capacitor's state or change it. As this form of memory is less expensive to produce than static RAM, it is the predominant form of computer memory used in modern computers.

16. RAM structure

17. Cash memory principles Cache memory is hidden from the programmer and appears as part of the system's memory space.It is simply a quantity of very high-speed memory that can be accessed rapidly by the processor. The element of magic comes from the ability of systems with cache memory to employ a tiny amount of high- speed memory (e.g., 128K bytes of cache memory in a system DRAM) and expect the processor to make over 95% of its accesses to the cache rather than to the much slower DRAM. The principal parameter of a cache system is its hit ratio, h, that defines the ratio of hits to all accesses. (Example with students tests)

18. Cache Organization There are three ways of organizing a cache memory: direct-mapped, associative mapped and set associative mapped cache. Direct-Mapped Cache The simplest way of organizing a cache memory employs direct mapping which relies on a simple algorithm to map data block i from the main memory into data block i in the cache. The smallest unit of data held in a cache is a line (or block) which is made up of typically 32 consecutive words.

19. Cash memory structure A cache memory requires a cache controller to determine whether or not the data currently being accessed by the CPU resides in the cache or whether it must be obtained from the main memory.

20. Modern cash memory hierarhy Here SM – single core (module) in multy-cored system, GPU – graphic unit (videoprocess or)

21. 21 Control questions 1. Structure of Motherboard of modern PC 2. Explain a principle of operation of the superscalar processor. 3. How does pipeline of Pentium works? 4. List all methods of improving of processors productivity. 5. Give an example of block-diagrams of moderm MP 6. Explain a principle of reordering of programs. 7. List groups of commands Pentium MMX 8. What processors provide parallelism of level commands?