1. LAYOUT DESIGN RULES
EMT251

2. LAYERS

3. DESIGN RULES

4. DESIGN RULES

5. DESIGN RULES

6. DESIGN RULES

7. DESIGN RULES

8. DESIGN RULES

9. Design Rule Checkers (DRC)
Goal: identify design rule violations
General approach: “scanline” algorithm
Computationally intensive, especially for large chips

10. Design Rule Checkers (DRC)
poly_not_fet to all_diff minimum spacing = 0.5 lambda.

11. Layout Versus Schematic (LVS)
Goal: Compare layout, schematic netlists
Compare transistors, connections (ignore parasitics)
Issue error if two netlists are not equivalent
Important for large designs

12. Layout Versus Schematic (LVS)DD
.subckt inv in out
MN1 Out In GND GND n L=0.4u W=1u
MN2 Out In VDD VDD p L=0.4u W=1u
.ends inv =
Out In
GND

13. Area Estimation
Length
GND In V DD
Width
Out
Area = Length x Width

14. The Challenge of Design
Start: higher level (spec)
Finish: lower level (implementation)
Must meet design criteria and constraints
Design time - how long did it take to ship a product?
Performance - how fast is the clock?
Cost - NRE (Non-Recurring Engineering) + unit cost
CAD tools - essential in modern design