Presentation is loading. Please wait.

Presentation is loading. Please wait.

ELEC 2200-002 Digital Logic Circuits Fall 2015 Logic Synthesis (Chapters 2-5) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and.

Published byVincent Turner Modified over 8 years ago

Similar presentations

Presentation on theme: "ELEC 2200-002 Digital Logic Circuits Fall 2015 Logic Synthesis (Chapters 2-5) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and."— Presentation transcript:

1 ELEC 2200-002 Digital Logic Circuits Fall 2015 Logic Synthesis (Chapters 2-5) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu Fall 2015, Nov 6... ELEC2200-002 Lecture 6 1

2 Logic Synthesis Definition: To design a logic circuit such that it meets the specifications and can be economically manufactured: Performance – meets delay specification, or has minimum delay. Cost – uses minimum hardware, smallest chip area, smallest number of gates or transistors. Power – meets power specification, or consumes minimum power. Testablility – has no redundant (untestable) logic and is easily testable. Fall 2015, Nov 6... ELEC2200-002 Lecture 6 2

3 Synthesis Procedure Minimization – Obtain MSOP or MPOS. This is also known as two-level minimization because the result can be implemented as a two-level AND-OR or NAND-NAND or NOR-NOR circuit. Technology mapping – Considering design requirements, transform the minimized form into one of the technologically realizable forms: Programmable logic array (PLA) Standard cell library Field programmable gate array (FPGA) Others... Fall 2015, Nov 6... ELEC2200-002 Lecture 6 3

4 References on Synthesis G. De Micheli, Synthesis and Optimization of Digital Circuits, New York: McGraw-Hill, 1994. S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill, 1994. Fall 2015, Nov 6... ELEC2200-002 Lecture 6 4

5 Programmable Logic Array (PLA) A direct implementation of multi-output function as a two-level circuit in MOS technology. PLA styles: NAND-NAND NOR-NOR Textbook, Chapter 5. Fall 2015, Nov 6... ELEC2200-002 Lecture 6 5

6 0 4 12 8 1 1 5 13 1 9 1 37 1 15 1 11 1 26 14 10 1 0 4 128 1 5 1 13 1 9 1 37 1 15 1 11 26 14 10 Example: Two-Output Function Need four products: P1, P2, P3, P4 Fall 2015, Nov 6... ELEC2200-002 Lecture 6 6 F1 A B C D F2 A B C D

7 Two-Level AND-OR Implementation Also known as technology-independent circuit. Fall 2015, Nov 6... ELEC2200-002 Lecture 6 7 A B C D F1 F2 P1 P2 P3 P4 INPUTSANDOR

8 INPUTSNAND NAND-NAND Implementation Fall 2015, Nov 6... ELEC2200-002 Lecture 6 8 A B C D F1 F2

9 A NAND Gate in nMOS Technology Fall 2015, Nov 6... ELEC2200-002 Lecture 6 9 VDD X Y XY GND VDD X Y XY GND VDD X Y XY GND R. C. Jaeger and T, N. Blalock, Microelectronic Circuit Design, Boston: McGraw-Hill, 2008, Section 6.8.2. Depletion load Enhancement load

10 NAND-NAND PLA Fall 2015, Nov 6... ELEC2200-002 Lecture 6 10 ABCD F1F2 VDD GND

11 NAND-NAND PLA SCHEMATIC Fall 2015, Nov 6... ELEC2200-002 Lecture 6 11 ABCDF1F2 INPUTS OUTPUTS AND-plane OR-plane Transistors at cross-points

12 Standard-Cell Design Obtain two-level minimized form. Map the design onto predesigned building blocks called standard cells (technology mapping). Standard-cell library contains predesigned logic cells in the technology of manufacture. Examples of technology: 90 nanometer CMOS 65 nanometer CMOS 45 nanometer CMOS... This is known as application-specific integrated circuit (ASIC). Fall 2015, Nov 6... ELEC2200-002 Lecture 6 12

13 Technology Mapping Find a common logic element, e.g., two-input NAND gate or inverter (one-input NAND). MSOP is converted into NAND-NAND circuit. Split larger input gates into two-input NAND gates and inverters. Cover the circuit with standard cells, also split into two-input NAND gates and inverters (graph-matching). Fall 2015, Nov 6... ELEC2200-002 Lecture 6 13

14 A Typical Cell Library NameArea units (cost)InputsOutput function, Z Inverter2A NAND23A, B NAND34A, B, C NAND45A, B, C, D AOI214A, B, C OAI214A, B, C AOI225A, B, C, D XOR4A, B Fall 2015, Nov 6... ELEC2200-002 Lecture 6 14 S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill 1994, Section 7.7, pp. 185-198.

15 NAND3 Cell in Transistors Fall 2015, Nov 6... ELEC2200-002 Lecture 6 15 ABCABC Z VDD GND

16 NAND3 Cell Graphs Fall 2015, Nov 6... ELEC2200-002 Lecture 6 16 Directed Acyclic Graph (DAG) (tree) Root ≡ Output One-input node (NOT) Two-input node (NAND)

17 NAND4 Cell Fall 2015, Nov 6... ELEC2200-002 Lecture 6 17

18 AOI21 Cell Fall 2015, Nov 6... ELEC2200-002 Lecture 6 18

19 OAI21 Cell Fall 2015, Nov 6... ELEC2200-002 Lecture 6 19

20 AOI22 Cell in Transistors Fall 2015, Nov 6... ELEC2200-002 Lecture 6 20 ABCDABCD VDD GND Z Observe that in a CMOS circuit, any vector of input variables connects the output Z either to GND or to VDD, giving it a value 0 or 1, respectively. Examining the pull-down network, we notice that the output is connected to GND if AB = 1 or CD =1. That gives the output function as,. The cell, therefore, is AOI22. Pull-up network Pull-down network

21 AOI22 Cell Fall 2015, Nov 6... ELEC2200-002 Lecture 6 21

22 XOR Cell Fall 2015, Nov 6... ELEC2200-002 Lecture 6 22

23 NAND Graphs for Library Cells NameArea units (cost)InputsNAND graph Inverter2A NAND23A, B NAND34A, B, C NAND45A, B, C, D AOI214A, B, C OAI214A, B, C AOI225A, B, C, D XOR4A, B Fall 2015, Nov 6... ELEC2200-002 Lecture 6 23

24 Technology Mapping Procedure Obtain MSOP. Convert to two-level AND-OR circuit. Transform to two-level NAND-NAND circuit. Transform to two-input NAND and inverter tree network. Perform an optimal pattern matching to obtain a minimum cost tree covering. Fall 2015, Nov 6... ELEC2200-002 Lecture 6 24

25 INPUTSNAND Previous Example: 2-Level NAND (Slide 8) Fall 2015, Nov 6... ELEC2200-002 Lecture 6 25 A B C D F1 F2

26 A Simple Technology Mapping Fall 2015, Nov 6... ELEC2200-002 Lecture 6 26 B C F1 F2 D A Cost = 24 NAND2 (3) NAND3 (4) (2) NAND2 (3)

27 Optimum Mapping: Convert NAND Circuit to Directed Acyclic Graph (DAG) Fall 2015, Nov 6... ELEC2200-002 Lecture 6 27 A B C D F1 F2 Each node is a NAND gate. (NOT ≡ 1-input NAND)

28 Split DAG into Trees (Forest) Fall 2015, Nov 6... ELEC2200-002 Lecture 6 28 A B C D F1 F2 D C B A D Cost = 24

29 Split Nodes With More Than Two Branches (Use NAND3, NAND4 Graphs) Fall 2015, Nov 6... ELEC2200-002 Lecture 6 29 ≡ or F2 ≡ NAND4 or

30 Uniform Branching (1 or 2) Fall 2015, Nov 6... ELEC2200-002 Lecture 6 30 A B C D F1 F2 C B D D A Cost = 32

31 Graph Matching Fall 2015, Nov 6... ELEC2200-002 Lecture 6 31 A B C D F1 F2 C B D D A NAND3 (4) OAI21 (4) NAND2 (3) (2) Cost = 22 Nodes inserted For pattern matching

32 Technology Mapping Fall 2015, Nov 6... ELEC2200-002 Lecture 6 32 A B C D F1 F2 C B D D A OAI21 (4) NAND3 (4) NAND2 (3) (2) Cost = 22 Inverters inserted For pattern matching (2)

33 Mapped Circuit Fall 2015, Nov 6... ELEC2200-002 Lecture 6 33 B C F1 F2 D A Cost = 22 NAND2 (3) NAND3 (4) (2) NAND2 (3) AOI21 (4)

34 Original Reference K. Keutzer, “DAGON: Technology Binding and Local Optimization by DAG matching,” Proc. 24th Design Automation Conf., 1987, pp. 341-347. Fall 2015, Nov 6... ELEC2200-002 Lecture 6 34

Download ppt "ELEC 2200-002 Digital Logic Circuits Fall 2015 Logic Synthesis (Chapters 2-5) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and."

Similar presentations

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Topics n Combinational logic functions. n Static complementary logic gate structures.

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Topics n Combinational logic functions. n Static complementary logic gate structures.
240-451 VLSI lecture, 2000 Lecture 4 MOS Circuits Department of Computer Engineering, Prince of Songkla University by Wannarat Suntiamorntut.

VLSI lecture, 2000 Lecture 4 MOS Circuits Department of Computer Engineering, Prince of Songkla University by Wannarat Suntiamorntut.
ELEC 2200-002 Digital Logic Circuits Fall 2014 Logic Synthesis (Chapters 2-5) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and.

ELEC Digital Logic Circuits Fall 2014 Logic Synthesis (Chapters 2-5) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and.
ELEC 2200-002 Digital Logic Circuits Fall 2008 Logic Minimization (Chapter 3) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and.

ELEC Digital Logic Circuits Fall 2008 Logic Minimization (Chapter 3) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and.
ECE 667 Synthesis and Verification of Digital Systems

ECE 667 Synthesis and Verification of Digital Systems
ECE 667 - Synthesis & Verification - Lecture 8 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Introduction.

ECE Synthesis & Verification - Lecture 8 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Introduction.
Spring 07, Feb 13 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Binary Decision Diagrams Vishwani D. Agrawal James.

Spring 07, Feb 13 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Binary Decision Diagrams Vishwani D. Agrawal James.
10/25/05ELEC 5970-001/6970-001 Lecture 151 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

10/25/05ELEC / Lecture 151 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
Combinational Circuits

Combinational Circuits
Spring 08, Jan 15 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Introduction Vishwani D. Agrawal James J. Danaher.

Spring 08, Jan 15 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Introduction Vishwani D. Agrawal James J. Danaher.
Technology Mapping.

Technology Mapping.
Spring 07, Jan 16 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Introduction Vishwani D. Agrawal James J. Danaher.

Spring 07, Jan 16 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Introduction Vishwani D. Agrawal James J. Danaher.
Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 12 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power.

Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 12 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power.
Spring 08, Feb 28 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Retiming Vishwani D. Agrawal James J. Danaher.

Spring 08, Feb 28 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Retiming Vishwani D. Agrawal James J. Danaher.
Fall 2006, Nov. 28 ELEC 5270-001/6270-001 Lecture 11 1 ELEC 5270-001/6270-001(Fall 2006) Low-Power Design of Electronic Circuits Power Analysis: High-Level.

Fall 2006, Nov. 28 ELEC / Lecture 11 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Power Analysis: High-Level.
10/13/05ELEC 5970-001/6970-001 Lecture 131 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

10/13/05ELEC / Lecture 131 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
10/11/05ELEC 5970-001/6970-001 Lecture 121 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

10/11/05ELEC / Lecture 121 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
Lecture 5 Multilevel Logic Synthesis

Lecture 5 Multilevel Logic Synthesis
Fall 2006, Oct. 5 ELEC 5270-001/6270-001 Lecture 8 1 ELEC 5270-001/6270-001(Fall 2006) Low-Power Design of Electronic Circuits Glitch-Free ASICs and Custom.

Fall 2006, Oct. 5 ELEC / Lecture 8 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Glitch-Free ASICs and Custom.
Fall 2006, Oct. 17 ELEC 5270-001/6270-001 Lecture 9 1 ELEC 5270-001/6270-001(Fall 2006) Low-Power Design of Electronic Circuits Power Analysis: Logic Level.

Fall 2006, Oct. 17 ELEC / Lecture 9 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Power Analysis: Logic Level.

Similar presentations

Ads by Google