1. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 1 Chapter 3a Instruction Sets: Characteristics and Functions

2. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 2 What is an Instruction Set? Defines many functions performed by processor. A programmer’s means of controlling the processor. The complete collection of instructions that are understood by a CPU Machine Code Binary Usually represented by assembly codes

3. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 3 Elements of an Instruction Operation code (Op code) –Do this Source Operand reference –To this Result Operand reference –Put the answer here Next Instruction Reference –When you have done that, do this... Operand - An entity on which operation is performed. reference - address What is an Instruction Set?

4. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 4 Main memory (or virtual memory or cache) CPU register I/O device Where have all the Operands Gone?

5. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 5 Instruction Cycle State Diagram

6. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 6 In machine code each instruction has a unique bit pattern For human consumption (well, programmers anyway) a symbolic representation is used –e.g. ADD, SUB, LOAD Operands can also be represented in this way –ADD A,B Instruction Representation

7. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 7 Simple Instruction Format

8. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 8 Data processing: Arithmetic and logic Instruction Data storage (main memory): memory Instruction Data movement (I/O): I/O Instruction Program flow control: Test and branch Instruction Instruction Types

9. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 9 One of traditional ways of describing processor architecture. 0-1-2 and 3 Addresses use Program Counter for next instruction. 4 addresses –May be a forth - Operand 1, Operand 2, Result and next instruction (usually implicit) –Not common –Needs very long words to hold everything 3 addresses –Operand 1, Operand 2, Result –a = b + c; Number of Addresses (a)

10. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 10 2 addresses –One address doubles as operand and result –a = a + b –Reduces length of instruction –Requires some extra work Temporary storage to hold some results Number of Addresses(b)

11. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 11 1 address –Implicit second address –Usually a register (accumulator) –Common on early machines Number of Addresses (c)

12. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 12 0 (zero) addresses –All addresses implicit –Uses a stack (top two), stack is a LIFO set of locations –e.g. c = a + b – push a – push b – add – pop c Stack – special memory organization Number of Addresses (d)

13. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 13 ExerciseExercise Given the following expression: c = a + b Using the zero address format, write the instructions and sketch the stack operation.

14. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 14 ?????????? f = a - b c + (d x e)

15. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 15 More addresses –More complex (powerful?) instructions –More registers Inter-register operations are quicker –Fewer instructions per program (Fig 10.3 p/g 325 stalling) Fewer addresses –Less complex (powerful?) instructions –More instructions per program –Faster fetch/execution of instructions How Many Addresses

16. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 16 Operation repertoire –How many ops? –What can they do? –How complex are they? Data types Instruction formats –Length of op code field –Number of addresses Instruction Set Design Decisions (1)

17. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 17 Registers –Number of CPU registers available –Which operations can be performed on which registers? Addressing modes RISC vs CISC Design Decisions (2)

18. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 18 Addresses Numbers –Integer/floating point Characters –Sequence of bits –ASCII (same as IRA)…etc. each character uses a unique 7-bit pattern, which leads to 128 different characters that can be represented in such manner. Logical Data –Bit-oriented view –Bits or flags IRA-international Reference Alphabet ASCII – American Standard Code for Information Interchange. Types of Operands

19. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 19 8 bit Byte 16 bit word 32 bit double word 64 bit quad word Addressing is by 8 bit unit A 32 bit double word is read at addresses divisible by 4 Pentium Data Types

20. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 20 General - arbitrary binary contents Integer - single binary value Ordinal - unsigned integer Unpacked BCD - One digit per byte Packed BCD - 2 BCD digits per byte Near Pointer - 32 bit offset within segment Bit field Byte String Floating Point Specific Data Types

21. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 21 Pentium Numeric Data Formats

22. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 22 8 (byte), 16 (halfword), 32 (word) and 64 (doubleword) length data types Some instructions need operand aligned on 32 bit boundary Can be big- or little-endian Fixed point processor recognises: –Unsigned byte, unsigned halfword, signed halfword, unsigned word, signed word, unsigned doubleword, byte string (<128 bytes) Floating point –IEEE 754 –Single or double precision PowerPC Data Types

23. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 23 Different machines, different op-codes. Some general types of operations are found in all machines. –Data Transfer –Arithmetic –Logical –Conversion –I/O –System Control –Transfer of Control Types of Operations

24. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 24 Specify –Source –Destination –Amount of data May be different instructions for different movements –e.g. IBM 370 Or one instruction and different addresses –e.g. VAX (MOVE), easier for the programmer but less compact as the IBM 370. Data Transfer

25. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 25 Add, Subtract, Multiply, Divide Signed Integer Floating point ? May include –Increment (a++) – add 1 to the operand –Decrement (a--) – subtract 1 from the operand –Negate (-a) –Absolute ( |a|) ArithmeticArithmetic

26. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 26 0 0000 Logical shift – the bits of a word is shifted left or right One end-bit shifted is lost Other end- a 0 is shifted in Arithmetic shift – treats the data as a signed integer and does not shift it sign bit. Right arithmetic shift –the sign bit is replicated into the bit position to its right. Left arithmetic shift -a logical left shift is performed on all bits but the sign bit, which is retained. Shift and Rotate Operations

27. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 27 Used for manipulating individual bits of a word or other addressable units Bitwise operations NOT AND – as a mask that selects certain bits OR - XOR – 1s complement EQUAL LogicalLogical

28. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 28 E.g. Binary to Decimal ConversionConversion

29. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 29 May be specific instructions May be done using data movement instructions (memory mapped) May be done by a separate controller (DMA) Input/OutputInput/Output

30. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 30 Privileged instructions CPU needs to be in specific state For operating systems use Systems Control

31. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 31 Branch –e.g. branch to x if result is zero Skip –e.g. increment and skip if zero –ISZ Register1 –Branch xxxx –ADD A Subroutine call –c.f. interrupt call CALL – transfer control to another location. Transfer of Control

32. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 32 BRZ 211 – Branch to 211 if result is zero. BR 202 Branch to 202 Branch Instruction

33. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 33 RETURN Call to Procedure Proc 1 Nested Procedure Calls

34. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 34 When execute a call, processor places the return address. Use of Stack

35. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 35 Stack Frame Growth Using Sample Procedures P and Q

36. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 36 What order do we read numbers that occupy more than one byte e.g. (numbers in hex to make it easy to read) 12345678 can be stored in 4x8bit locations as follows Byte Order ; A portion of chips?

37. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 37 AddressValue (1)Value(2) 1841278 1853456 1865634 1877812 i.e. read top down or bottom up? Byte Order (example)

38. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 38 The problem is called Endian The system on the left has the least significant byte in the lowest address This is called big-endian The system on the right has the least significant byte in the highest address This is called little-endian Byte Order Names

39. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 39 Example of C Data Structure

40. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 40 Alternative View of Memory Map

41. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 41 Pentium (80x86), VAX are little-endian IBM 370, Motorola 680x0 (Mac), and most RISC are big-endian Internet is big-endian –Makes writing Internet programs on PC more awkward! –WinSock provides htoi and itoh (Host to Internet & Internet to Host) functions to convert Standard…What Standard?

42. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 42 Chapter 3b: Instruction Sets: Addressing Modes and Formats Computer Architecture

43. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 43 The address fields are relatively small There is a trade off between address range and addressing flexibility Two notes: 1) Most architectures provide more than one mode. Either Different opcodes use different modes, or one or more bits in instruction will tell which mode to use. 2) Effective address (EA) will be main memory or register, if virtual memory it will be either virtual address or register Addressing Modes (1)

44. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 44 Immediate Direct Indirect Register Register Indirect Displacement (Indexed) Stack Addressing Modes (2)

45. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 45 Immediate Addressing Operand is part of instruction Operand in the address field e.g. ADD 5 –Add 5 to contents of accumulator –5 is operand No memory reference to fetch data Fast Limited range Remember !!! Operand - An entity on which operation is performed.

46. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 46 OperandOpcode Instruction Immediate Addressing

47. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 47 Direct Addressing Address field contains address of operand Effective address, EA = A e.g. ADD A –Look in memory at address A for operand –Add contents of cell A to accumulator Single memory reference to access data No additional calculations to work out effective address Limited address space Length of address field is less often than the word length

48. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 48 Address AOpcode Instruction Memory Operand Single memory reference Direct Addressing

49. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 49 Memory cell pointed to by address field contains the address of (pointer to) the operand Operand in memory cell pointed to by address field in memory. EA = (A) –Look in A, find address (A) and look there for operand e.g. ADD (A) –Add contents of cell pointed to by contents of A to accumulator Indirect Addressing

50. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 50 Address AOpcode Instruction Memory Operand Pointer to operand Indirect Addressing

51. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 51 Large address space 2 n where n = word length May be nested, multilevel, cascaded –e.g. EA = (((A))) Draw the diagram yourself Multiple memory accesses to find operand (one to get its address and another to get its value) Hence slower Indirect Addressing

52. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 52 Operand is held in register named in address field EA = R Disadvantage: Limited number of registers Advantages: –Shorter instructions (Very small address field needed) –Faster instruction fetch Register Addressing

53. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 53 Register Addressing (2) No memory access Very fast execution Very limited address space General Purpose registers helps performance –Requires good assembly programming or compiler writing Similar to direct addressing except that address field refers to register rather than main memory

54. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 54 Register Address ROpcode Instruction Registers Operand Register Addressing

55. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 55 Similar to indirect addressing except that address field refers to register rather than main memory EA = (R) Operand is in memory cell pointed to by contents of register R Large address space (2 n ) One fewer memory access than indirect addressing Register Indirect Addressing

56. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 56 Register Address ROpcode Instruction Memory Operand Pointer to Operand Registers Register Indirect Addressing

57. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 57 Very powerful mode (combines capabilities of direct addressing and register indirect addressing) EA = A + (R) Address field hold two values –A = base value –R = register that holds displacement –or vice versa Displacement Addressing

58. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 58 Register ROpcode Instruction Memory Operand Pointer to Operand Registers Address A + EA EA = A + (R) Displacement Addressing

59. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 59 A version of displacement addressing R = Program counter, PC EA = A + (PC) i.e. get operand from A cells from current location pointed to by PC Principal of locality of reference & cache usage Relative Addressing

60. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 60 A holds displacement R holds pointer to base address R may be explicit or implicit e.g. segment registers Base-Register Addressing

61. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 61 A holds pointer to base address R holds displacement EA = A + R Good for accessing arrays (list) EA = A + R R++ Indexed Addressing

62. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 62 Postindex EA = (A) + (R) Preindex EA = (A+(R)) CombinationsCombinations

63. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 63 Operand is (implicitly) on top of stack e.g. –ADDPop top two items from stack and add Refer Stallings p/g 362 Stack Addressing

64. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 64 Pentium Addressing Modes Virtual or effective address is offset into segment –Starting address plus offset gives linear address –This goes through page translation if paging enabled 12 addressing modes available –Immediate –Register operand –Displacement –Base –Base with displacement –Scaled index with displacement –Base with index and displacement –Base scaled index with displacement –Relative

65. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 65 Perform further study on addressing modes in Pentium and PowerPC processor

66. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 66 Pentium Addressing Mode Calculation

67. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 67 PowerPC Addressing Modes Load/store architecture –Indirect Instruction includes 16 bit displacement to be added to base register (may be GP register) Can replace base register content with new address –Indirect indexed Instruction references base register and index register (both may be GP) EA is sum of contents Branch address –Absolute –Relative –Indirect Arithmetic –Operands in registers or part of instruction –Floating point is register only

68. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 68 PowerPC Memory Operand Addressing Modes

69. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 69 Instruction Formats Layout of bits in an instruction Includes opcode Includes (implicit or explicit) operand(s) Usually more than one instruction format in an instruction set

70. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 70 Instruction Length Affected by and affects: –Memory size –Memory organization –Bus structure –CPU complexity –CPU speed Trade off between powerful instruction repertoire and saving space

71. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 71 Allocation of Bits Number of addressing modes Number of operands Register versus memory: With a single user-visible register (accumulator), requires many instructions. The more registers are used for operands references the fewer bits are needed. Most machines have 32 registers. Number of register sets Address range: Direct addressing rarely used. Address granularity: In a system with 16 or 32 bits words, an address can reference a word or a byte at the designer’s choice (Bytes good for character manipulation).

72. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 72 PDP-8 Instruction Format

73. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 73 PDP-8 Instruction Format Each memory reference consists of 7 bits, thus the memory is divided into fixed length frames of 2^7=128 words each.

74. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 74 PDP-10 Instruction Format Was designed to be a large scale time shared system, making the system easy to program. Orthogonality: Is a principle by which two variables are independent from one another. PDP-10 designers use this term to tell that an address is always computed independently of the opcode.

75. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 75 PDP-11 Instruction Format Uses a set of eight 16 bit general purpose registers, two of which are used as a stack an the other as PC.

76. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 76 VAX Instruction Examples

77. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 77 Pentium Instruction Format

78. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 78 PowerPC Instruction Formats (1)

79. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 79 PowerPC Instruction Formats (2)