1. University of Connecticut Virtual Lab Carl DiFederico, Shane Tobey, Kasim Ward Graduate Student Advisor: Qihang Shi Senior Faculty Advisor: Mohammed Tehranipoor Electrical & Computer Engineering

2. All Rights Reserved 2 Hardware Design Moving Forward This weekend we wish to begin ordering parts for benchmarking Is the purchase procedure the same as before? We wish to burn-age an acceptable percentage of chips We have several models to be decided from regarding how we connect the boards

3. All Rights Reserved 3 Scan-Chain Option Problem Leakage and transient current are analog signals, and will damp over long distance, causing DUT farther away to be damped more than DUT closer to probe in a daisy-chain connection One set of instruments for each DUT infeasible

4. All Rights Reserved 4 Tree Signal Path Tree-like connection for analog signal path, and signal amplification on each board for incoming signal

5. All Rights Reserved 5 Analog Signal Path Use an extra board as an expandable control interface from FPGA and Oscilloscope to DUT boards This equalizes noise, removes the need for amplification and removes the need to relay the probe

6. All Rights Reserved 6 Upcoming Deadlines and Goals Begin parts ordering for cleaning up the board 8051 Burn test Sep 30 (M) Project Specifications Due