1. 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski ralphm@engr.smu.edu Peter-Michael Seidel seidel@engr.smu.edu Southern Methodist University Dallas, TX 75275 Computer Science and Engineering

2. 2 SDV SMU Dynamic Verilog Visualization HDLs Schematic Entry Waveform Text

3. 2 SDV SMU Dynamic Verilog Visualization HDL Design SDV 2 Schematic Visualization Text Based Values/Time Dynamic Signal Propagation Simulation StructureFunctionality

4. 2 SDV SMU Dynamic Verilog Visualization Syntax-Error Free Verilog Hardware Description Structural, Behavioral, or Mixed Physically Feasible Design SDV 2

5. 2 SDV SMU Dynamic Verilog Visualization Visualization Configuration Module Selection Module Placement / Geometry Port Orientation Lines Customization SDV 2

6. 2 SDV SMU Dynamic Verilog Visualization Veriwell 2.3 Command Line Simulator Visualization Signal Propagation Text Output Visualization and Animation Front-End Visualization Configuration SDV 2

7. 2 SDV SMU Dynamic Verilog Visualization SIMULATION APPROACH 2 Bit Ripple Carry Adder Independent Atomic Module Simulations with Dynamic Variable Initialization vs. Complete System Simulation

8. 2 SDV SMU Dynamic Verilog Visualization SIMULATION APPROACH 2 Bit Ripple Carry Adder Independent Atomic Module Simulations with Dynamic Variable Initialization vs. Complete System Simulation

9. 2 SDV SMU Dynamic Verilog Visualization SIMULATION APPROACH 2 Bit Ripple Carry Adder Independent Atomic Module Simulations with Dynamic Variable Initialization vs. Complete System Simulation

10. 2 SDV SMU Dynamic Verilog Visualization SIMULATION APPROACH 2 Bit Ripple Carry Adder Independent Atomic Module Simulations with Dynamic Variable Initialization vs. Complete System Simulation

11. 2 SDV SMU Dynamic Verilog Visualization MODULE SIMULATION ORDER { Direct Connection Continuous/Procedural Assignment Function/Task Primitive/User Defined Primitive Output  Input Dependencies Simulation Order Availability of Variables at Time Of Independent Module Simulation Determine Guarantees

12. 2 SDV SMU Dynamic Verilog Visualization MODULE SIMULATION ORDER EXTRACTION 2 Step Extraction Procedure 1.Local Dependency Dependency Among Instantiations in a Defined Module 2.Global Dependency Dependency Considering The Entire System Local Input/Output Instantiation Dependency Top-Level

13. 2 SDV SMU Dynamic Verilog Visualization MODULE SIMULATION ORDER In-Order Traversal Generates the Simulation Order 1. During Visit- inputs to the Instantiation are known Local Input/Output Instantiation Dependency Top-Level

14. 2 SDV SMU Dynamic Verilog Visualization MODULE SIMULATION ORDER Local Input/Output Instantiation Dependency Top-Level 2. Return Visit- all inputs from the module’s instantiations are known

15. 2 SDV SMU Dynamic Verilog Visualization MODULE SIMULATION ORDER Local Input/Output Instantiation Dependency Top-Level 2. Return Visit- all inputs from the module’s instantiations are known 3. Final Return - all Values within the Module are resolved.

16. 2 SDV SMU Dynamic Verilog Visualization MODULE SIMULATION ORDER Local Input/Output Instantiation Dependency Top-Level S – Total Simulations/time unit I – Total instantiations within module i

17. 2 SDV SMU Dynamic Verilog Visualization VARIABLE INTIALIZATION AND EVENT EXTRACTION Variable Initialization Event Extraction Dynamically Created Top Level Modules.V Event Monitoring always@ Statements

18. 2 SDV SMU Dynamic Verilog Visualization VARIABLE INTIALIZATION AND EVENT EXTRACTION Variable Initialization Event Extraction Dynamically Created Top Level Modules.V t-1 t value initial begin #1 end t (event) = t (SDVV) + t (Veriwell) -1

19. 2 SDV SMU Dynamic Verilog Visualization VARIABLE INTIALIZATION AND EVENT EXTRACTION Variable Initialization Event Extraction.V t (event) = t (SDVV) + t (Veriwell) -1 Static Module Definition Veriwell.V.log Events Log File

20. 2 SDV SMU Dynamic Verilog Visualization OPTIMIZATIONOPTIMIZATION Number Of Simulations / time unit Data Structures Searching/Sorting INTERFACE Graphics Enhancement Visualization Configuration Text Editor Error Detection

21. 2 SDV SMU Dynamic Verilog Visualization LIBRARY Extension of Verilog HDL for Animation of Dynamically Re-configurable Systems Static Module Definitions DEMO

22. 2 SDV SMU Dynamic Verilog Visualization SDV Homepage www.engr.smu.edu/~ralphm/sdvv Ralph Marczynski ralphm@engr.smu.edu Peter-Michael Seidel seidel@engr.smu.edu 2 Marczynski’s Homepage www.engr.smu.edu/~ralphm THANK YOU