1. Performance of Silicon Pixels at -5 & -10 C after Radiation Daniela Bortoletto Gino Bolla Amitava Roy Carsten Rott

2. Irradiation at IUCF We irradiated 5 chips from Sintef wafer 9 (7,39,42,44,46) at Indiana University Cyclotron Facility on 30th November. Pixel 7,44 and 46 are baseline design. Pixel 42 spiral ring and pixel 39 single ring design. Pixel 7,39,42 and 46 were exposed to a fluence of 1x10 14 p/c.m. 2. Pixel 44 were exposed to 6x10 14 p/c.m. 2 Measurement was done at -5 0 & -10 0 C.

3. Pixel 46 Design A Fluence -1x10 14

4. Pixel 44 Design A Fluence -6x10 14

5. Pixel 7 Design A Fluence -1x10 14

6. Pixel 39 Design B Fluence -1x10 14 10nA/pixel 100nA/pixel

7. Pixel 42 Design D Fluence -1x10 14

8. Pixel 7 - Depletion Voltage Design A Fluence -1x10 14 Full Depletion at 33 V

9. Summary Pixel arrays 7,39,42,46, which were exposed to a fluence of 1x10 14 p/c.m. 2, deplete around 35 volts. At -10 0 C average leakage current at depletion voltage is 0.71  A (1.1nA/pixel). At -10 0 C leakage current per pixel reaches 10nA at 340V, 322V, 402V and 392V for pixel arrays 7,39,42 and 46 respectively. We could not measure depletion voltage for the pixel array 44 which was exposed to fluence of 6x10 14 p/c.m. 2. At -10 0 C leakage current per pixel reaches 10nA at 298V for pixel array 44. We plan to bump bond this pixel arrays to chip and to measure them with source.