1. Large Signal behavior of metal-oxide-semiconductor field effect transistor

2. Metal-oxide-semiconductor field-effect transistors (MOSFETs) allow high density and low power dissipation.
To reduce system cost and increase portability, both increased levels of integration and reduced power dissipation are required.
One way to achieve these goals is to use a processing technology that provides both bipolar and MOS transistors, allowing great design flexibility.
All-MOS processes are less expensive than combined bipolar and MOS processes.

3. Transfer Characteristics of MOS Devices
Heavily doped n-type source and drain regions are fabricated in a p-type substrate.
A thin layer of silicon dioxide is grown over the substrate material and a conductive gate material (metal or polycrystalline silicon) covers the oxide between source and drain.

4. In operation, the gate-source voltage modifies the conductance of the region under the gate, allowing the gate voltage to control the current flowing between source and drain.
The term enhancement mode refers to the fact that no conduction occurs for VGS= 0.
Thus, the channel must be enhanced to cause conduction. MOS devices can also be made by using an n-type substrate with a p-type conducting channel. Such devices are called enhancement-mode p-channel MOS (PMOS) transistors.
The derivation begins by noting that with VGS = 0, the source and drain regions are separated by back-to-back pn junctions.

5. Now consider the substrate, source, and drain grounded with a positive voltage VGS applied to the gate as shown.
The gate and substrate then form the plates of a capacitor with the SiO2 as a dielectric. Positive charge accumulates on the gate and negative charge in the substrate.

6. The charge per area in this depletion region is
The depletion-layer width X under the oxide is
φ potential in the depletion layer at the oxide-silicon interface,
NA doping density of the p-type substrate,
E permittivity of the silicon.
The charge per area in this depletion region is
When the surface potential reaches a critical value equal to twice the Fermi level φf, a phenomenon known as inversion occur.
The Fermi level φf is defined as
where kBoltzmann's constant.

7. niintrinsic carrier concentration,
Egband gap of silicon,
Nc density of allowed states near the edge of the conduction band, Nv density of allowed states near the edge of the valence band.
The Fermi level φf is usually about 0.3 V.
Inversion produces a continuous n-type region with the source & drain regions and forms the conducting channel between source & drain.
In the presence of an inversion layer, and without substrate bias, the depletion region contains a fixed charge density

8. If a substrate bias voltage VSB is applied between the source and substrate, the potential required to produce inversion becomes (2 φf + VSS), and the charge density stored in the depletion region in general is
The gate-source voltage VGS required to produce an inversion layer is called the threshold voltage Vt. This voltage consists of 3 components.
A voltage [2 φf + (Qb/Cox)] to sustain the depletion-layer charge Qb,
where Cox gate oxide capacitance per unit area.
A work-function difference φms, exists between the gate metal and the silicon.
A positive charge density Qs, always exists in the oxide at the silicon interface. This charge is caused by crystal discontinuities at the Si - Si02 interface and must be compensated by a gate-source voltage contribution of - QSS /Cox.

9. Thus we have a threshold voltage
Vt0 is the threshold voltage with VSB = 0.
The parameter γ is defined as
And
where εox permittivity,
tox thickness of the oxide.

10. dt time required for this charge to cross length dy. The charge dQ is
The drain current ID is
where dQ incremental channel charge at a distance y from the source in an incremental length dy of the channel,
dt time required for this charge to cross length dy.
The charge dQ is

11. where W width of the device perpendicular to the plane and
QI induced electron charge per unit area of the channel.
At a distance y along the channel, the voltage with respect to the source is V(y) and the gate-to-channel voltage at that point is VGS - V(y).
We assume this voltage exceeds the threshold voltage Vt. Thus the induced electron charge per unit area in the channel is
And,
where vd electron drift velocity at a distance y from the source.
The drift velocity is determined by the horizontal electric field.

12. When the horizontal electric field ξ(y) is small, the drift velocity is proportional to the field and
Where µn average electron mobility in the channel.
The mobility depends on both the temperature and the doping level.
Also, µn is sometimes called the surface mobility for electrons because the channel forms at the surface of the silicon.
The electric field ξ(y) is
where dV incremental voltage drop along the length of channel dy at a distance y from the source.

13. Separating variables and integrating gives
Carrying out this integration gives
Where
When VDS << 2(VGS - Vt), ID is approximately proportional to VDS.
As the value of VDS is increased, the induced conducting channel narrows at the drain end and Q, at the drain end approaches zero as VDS approaches (VGS - Vt).

14. That is, the channel is no longer connected to the drain when
VDS > VGS – Vt. This phenomenon is called pinch-off.
Therefore, when VDS = VGS - Vt,
W.K.T,
The drain current in the pinch-off region varies slightly as the drain voltage is varied.
If this depletion-layer width is Xd, then the effective channel length

15. Current in the pinch-off region,
Xd and Leff are functions of the drain-source voltage in the pinch-off region, ID varies with VDS. This effect is called channel-length modulation.
And thus
The Early voltage can be defined as

16. and thus
For MOS transistors, channel-length modulation is the reciprocal of the Early voltage,
Including channel-length modulation,
Plots of ID versus VDS with VGS shown for an NMOS transistor.

17. The device operates in the pinch-off region when VDS > (VGS - Vt).
The pinch-off region for MOS devices is often called the saturation region.
In saturation, the output characteristics are almost flat, which shows that the current depends mostly on the gate-source voltage.
When VDS < (VGS - Vt), the device operates in the Ohmic or triode region, where the device can be modeled as a nonlinear voltage-controlled resistor connected between the drain and source.
The resistance of this resistor is nonlinear . Since VDS 2 term is small when VDS is small, the nonlinearity is also small and the ohmic region is also sometimes called the linear region.
The boundary between the ohmic and saturation regions occurs when
VDS = (VGS - Vt)

18. Decomposition of Gate-Source Voltage
The gate-source voltage of a given MOS transistor is usually separated into two parts:
the threshold, Vt,
the voltage over the threshold, VGS – Vt (overdrive).
Assuming square-law behavior, the overdrive is

19. Threshold Temperature Dependence
Assume that Φms, Qss, and Cox, are independent of temperature.
Then Differentiating,
Assume that the VSB= 0.

20. Assume both Nc and Nv, are independent of temperature.
Then differentiating gives
Equation shows that the threshold voltage falls with increasing temperature if φf < Eg/(2q).