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Gigabit Kits Workshop January 2001 1 Washington WASHINGTON UNIVERSITY IN ST LOUIS Higher-Level Data Processing on the FPX Applied Research Laboratory Washington.

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Presentation on theme: "Gigabit Kits Workshop January 2001 1 Washington WASHINGTON UNIVERSITY IN ST LOUIS Higher-Level Data Processing on the FPX Applied Research Laboratory Washington."— Presentation transcript:

1 Gigabit Kits Workshop January 2001 1 Washington WASHINGTON UNIVERSITY IN ST LOUIS Higher-Level Data Processing on the FPX Applied Research Laboratory Washington University, St. Louis http://www.arl.wustl.edu/arl/projects/fpx florian@arl.wustl.edu

2 Gigabit Kits Workshop January 2001 2 Washington WASHINGTON UNIVERSITY IN ST LOUIS Motivation FPX interface is cell based Higher level protocols use packets with arbitrary length HL protocols use checksums/CRC for data integrity Common jobs for all applications (check HEC, control cells)  Provide interface for higher level data processing

3 Gigabit Kits Workshop January 2001 3 Washington WASHINGTON UNIVERSITY IN ST LOUIS The wrapper concept

4 Gigabit Kits Workshop January 2001 4 Washington WASHINGTON UNIVERSITY IN ST LOUIS The Cell-Processor Checks the HEC and drops erroneous cells Dispatch cells to application or bypass Handles control cells Recomputes HEC for outgoing cells

5 Gigabit Kits Workshop January 2001 5 Washington WASHINGTON UNIVERSITY IN ST LOUIS Control Cell Processing Checks control cell CRC Filters control cells sent to this module Buffers control cell payload Multiplexes response cells from several subprocesses Generates CRC on outgoing response cells

6 Gigabit Kits Workshop January 2001 6 Washington WASHINGTON UNIVERSITY IN ST LOUIS Generic Control Cell Processor Provides common interface for OpCode processing Handles default OpCodes:  0x00 Generic Probe Response (“Generic Cell Processor Version 1.0”)  0x02/0x04 Set /Read VPI/VCI register

7 Gigabit Kits Workshop January 2001 7 Washington WASHINGTON UNIVERSITY IN ST LOUIS AAL5 Encapsulation Payload is packed in cells Padding may be added 64 bit Trailer at end of cell Trailer contains CRC-32 Last Cell indication bit (last bit of PTI field)

8 Gigabit Kits Workshop January 2001 8 Washington WASHINGTON UNIVERSITY IN ST LOUIS AAL5 Frame Processor Frame Processor detects frame boundaries FP handles CRC FP segments data into cells

9 Gigabit Kits Workshop January 2001 9 Washington WASHINGTON UNIVERSITY IN ST LOUIS FP – Application Interface Cell based transmission (FPX) Data Start of Cell (SOC) Last Cell information in ATM header Congestion Control (TCA) Frame based transmission (FP) Data Start of Frame (SOF) Data Enable (DataEn) End of Frame (EOF) Congestion Control (TCA) Additional information is sent after SOF and EOF

10 Gigabit Kits Workshop January 2001 10 Washington WASHINGTON UNIVERSITY IN ST LOUIS Frame Processor Timing

11 Gigabit Kits Workshop January 2001 11 Washington WASHINGTON UNIVERSITY IN ST LOUIS Data Processing on the fly Data is immediately processed when it comes in  First payload can already been sent when CRC is available  Errors must be preserved in error case while CRC must be adapted in correct case

12 Gigabit Kits Workshop January 2001 12 Washington WASHINGTON UNIVERSITY IN ST LOUIS Replacing the CRC Compute CRC-32 on Payload and Padding Use XOR Operation on computed and transmitted CRC Replace CRC field in cell

13 Gigabit Kits Workshop January 2001 13 Washington WASHINGTON UNIVERSITY IN ST LOUIS Error- and non-error Case

14 Gigabit Kits Workshop January 2001 14 Washington WASHINGTON UNIVERSITY IN ST LOUIS Current limitations Frame length is still fixed Data must be sent according to cell structure DataEnable is also hi on padding

15 Gigabit Kits Workshop January 2001 15 Washington WASHINGTON UNIVERSITY IN ST LOUIS IP Processor Verify IP version Check Header Checksum for application Signal start of payload (SOP) Decrease TTL field (ev. Drop)

16 Gigabit Kits Workshop January 2001 16 Washington WASHINGTON UNIVERSITY IN ST LOUIS IP-Processor Timing

17 Gigabit Kits Workshop January 2001 17 Washington WASHINGTON UNIVERSITY IN ST LOUIS UDP Processor Check for protocol ID (17) Signal start of datagram (SOD) Handle UDP checksum

18 Gigabit Kits Workshop January 2001 18 Washington WASHINGTON UNIVERSITY IN ST LOUIS UDP-Processor Timing

19 Gigabit Kits Workshop January 2001 19 Washington WASHINGTON UNIVERSITY IN ST LOUIS Current limitations IP Processor  IP options are not recognized  No ICMP message is generated if TTL check fails UDP Processor  UDP checksum is set to zero (“debug”)

20 Gigabit Kits Workshop January 2001 20 Washington WASHINGTON UNIVERSITY IN ST LOUIS Summary & Conclusions Convenient interface for higher level data processing Applications can concentrate on their data Common jobs are done by standard modules You can choose level of abstraction


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