1. PC Based Spectrum Analyzer April 29, 2003 May03-10 Faculty Advisor: Dr. DJ Chen Michael Cain Paul Heil Eric Rasmussen Aung Thuya Client: Teradyne Inc. Phase III

2. The team would like to thank: Teradyne Steve Miller Dr. Degang Chen Acknowledgements

3. Problem Statement Operating Environment Intended Use and Users Assumptions and Limitations End Product Accomplishments Approaches Research Design Implementation Testing Resources and Schedules Closing Materials Presentation Outline

4. List of Definitions DAC – digital to analog converter DC offset – DC voltage in an AC signal FPGA – field programmable gate array Spectrum analyzer – measures magnitude of signal harmonics THD – total harmonic distortion

5. 100MHz high gain, low noise, low distortion Programmable DC offset and frequency response calibration Amplifier for PC Based Spectrum Analyzer Problem Statement

6. DC — 1kHz+/- 5 volts6, 20, 40, 60+/- 10 volts0.05 dB< - 105 dB1.5 nV/rtHz > 1kHz - 20 kHz+/- 5 volts6, 20, 40, 60+/- 10 volts0.05 dB< - 95 dB1.5 nV/rtHz > 20kHz - 100kHz+/- 2.5 volts6, 20, 40+/- 5 volts0.10 dB< -85 dB2.5 nV/rtHz > 100kHz - 1MHz+/- 2.5 volts6, 20, 40+/- 5 volts0.10 dB< - 80 dB3.5 nV/rtHz > 1MHz - 10MHz+/- 2.5 volts6, 20, 40+/- 5 volts0.10 dB< - 70 dB3.5 nV/rtHz > 10MHz - 20MHz+/- 2.5 volts6, 20+/- 5 volts0.10 dB< -65 dB3.5 nV/rtHz > 20MHz - 50MHz+/- 1.0 volts6, 20+/- 2.0 volts0.10 dB< -50 dB5.0 nV/rtHz > 50MHz - 100MHz+/- 1.0 volts6, 20+/- 2.0 volts0.10 dB< -40 dB5.0 nV/rtHz Input Total InputVoltageAvailableMax Output Freq ResponseHarmonic FrequencyRange Gain SettingsVoltageFlatnessDistortionNoise Range(Volts)(dB)(Volts)(dB) (nV/rtHz) Problem Statement (cont’d.)

7. Normal lab conditions Low humidity, room temperature Operating Environment

8. Intended Users and Uses Users will be Teradyne test engineers Use will be preamplifier for PC Based spectrum analyzer

9. Users Teradyne test engineers are familiar with the operation of a spectrum analyzer Requirements Specifications are attainable Financial Budget Teradyne will cover project costs Assumptions

10. Hardware Noise and distortion trade-off Must have a stable configuration Software Simulation software limitations Technical Knowledge No experience with PC board fabrication Limitations

11. The end product will consist of the following deliverables: Analog amplifier design with embedded digital controls Software for the embedded digital controls Design and user documentation End Product

12. Research – 100% completed Analog amplifier design – 100% completed Digital controls – 100% completed Software controls – 100% completed Simulations – 100% completed Fabrication – 0% completed Testing – 0% completed Present Accomplishments

13. Amplifier Topology Low noise amplifier (LNA) Operational amplifier in resistive feedback Approaches Considered and Used

14. DC Offset Correction Clocked ping-pong structure Offset voltage referral Successive approximation scheme Approaches Considered and Used (cont’d.)

15. Frequency Response Calibration Automatic Manual Approaches Considered and Used (cont’d.)

16. Project Definition Activities Project scope was changed to a paper design Occurred after design was submitted for fabrication Will be completed by future team

17. Amplifier Topologies Operational Amplifiers DACs FPGAs Digital Potentiometers Comparators Research Activities

18. Amplifier Design Design Activities

19. Design Activities (cont’d.)

21. DC offset correction Design Activities (cont’d.)

22. Frequency response calibration

23. Design Activities (cont’d.)

24. Implementation Activities Implementation was not necessary

25. PSpice simulations for analog design Verilog simulations for digital state machine Testing Activities

26. Other Significant Activities User manual Estimated performance analysis Design vault on CD

27. Resource Requirements Personal Effort

28. Resource Requirements (cont’d.) ItemTeam HoursOther HoursCost Board Fabrication00$0 Components00$0 Project Poster100$48 Total100$48 Total Cost

29. Project Schedule Schedule

30. Schematic level implementation – fully met Simulations – fully met Fabrication – not attempted Testing – not attempted Project Evaluation

31. Only one will be fabricated for testing purposes Will be a part of Teradyne’s Integra J750 Cost of J750 starts at $99,000 Commercialization

32. Meet low noise requirement Make frequency response calibration automatic Fabricate board Complete testing Recommendations for Future Work

33. Set up weekly meetings with client and team Do not procrastinate Make sure design tools are adequate Do not be too optimistic with scheduling Do not be too elaborate with complicated designs Lessons Learned

34. Losing a team member No available times for meetings Parts ordered on time Sending design to fabrication on time Risk and Risk Management

35. Closing Summary Learned a lot about amplifier topologies Team skills improved Useful information passed to next group

36. Questions?