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Published byAnnabelle Griffith Modified over 8 years ago
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The System Bus
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Conceptual CPU Block Diagram Datapath Regs Buses ALU Control Unit Bus Interface IR etc. PC etc. Control Signals Status Signals PSR System Bus Data Addr Control Sequencing and Timing Logic
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CPU System Bus Data Addr Control
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CPU System Bus Data Bus D0-D31 Address Bus A0-A31 Control Bus 32
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CPU Input/ Output Memory Single-Bus System: Simplified Block Diagram Data Bus Address Bus Control Bus System Bus 32
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CPU Input/ Output Memory Data Bus Address Bus Control Bus System Bus 32 Address Obj Code Source Code 00000804 c2002db0 ld [x], %r1.... 00000db0 fffffffe x:.word -2
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Read Cycle Bus Timing (Synchronous Bus) Clock ( ) Time _____ MREQ ___ RD ADDR ?Valid? ___ WR DATA Valid??
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Write Cycle Bus Timing (Synchronous Bus) Clock ( ) Time _____ MREQ ___ RD ADDR ?Valid? ___ WR DATA Valid??
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Address Obj Code Source Code 00000804 c2002db0 ld [x], %r1.... 00000db0 fffffffe x:.word -2
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