1. C OMPUTER O RGANIZATION AND D ESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor

2. Chapter 4 — The Processor — 2 Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified version A more realistic pipelined version Simple subset, shows most aspects Memory reference: lw, sw Arithmetic/logical: add, sub, and, or, slt Control transfer: beq, j §4.1 Introduction

3. Chapter 4 — The Processor — 3 Instruction Execution PC  instruction memory, fetch instruction Register numbers  register file, read registers Depending on instruction class Use ALU to calculate Arithmetic result Memory address for load/store Branch target address Access data memory for load/store PC  target address or PC + 4

4. Chapter 4 — The Processor — 4 CPU Overview

5. Chapter 4 — The Processor — 5 Multiplexers Can’t just join wires together Use multiplexers

6. Chapter 4 — The Processor — 6 Control

7. Chapter 4 — The Processor — 7 Logic Design Basics §4.2 Logic Design Conventions Information encoded in binary Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses Combinational element Operate on data Output is a function of input State (sequential) elements Store information

8. Chapter 4 — The Processor — 8 Combinational Elements AND-gate Y = A & B A B Y I0 I1 Y MuxMux S Multiplexer Y = S ? I1 : I0 A B Y + A B Y ALU F Adder Y = A + B Arithmetic/Logic Unit Y = F(A, B)

9. Chapter 4 — The Processor — 9 Sequential Elements Register: stores data in a circuit Uses a clock signal to determine when to update the stored value Edge-triggered: update when Clk changes from 0 to 1 D Clk Q D Q

10. Chapter 4 — The Processor — 10 Sequential Elements Register with write control Only updates on clock edge when write control input is 1 Used when stored value is required later D Clk Q Write D Q Clk

11. Chapter 4 — The Processor — 11 Clocking Methodology Combinational logic transforms data during clock cycles Between clock edges Input from state elements, output to state element Longest delay determines clock period

12. Chapter 4 — The Processor — 12 Building a Datapath Datapath Elements that process data and addresses in the CPU Registers, ALUs, mux’s, memories, … We will build a MIPS datapath incrementally Refining the overview design §4.3 Building a Datapath

13. Chapter 4 — The Processor — 13 Instruction Fetch 32-bit register Increment by 4 for next instruction

14. Chapter 4 — The Processor — 14 R-Format Instructions Read two register operands Perform arithmetic/logical operation Write register result

15. Register File Chapter 4 — The Processor — 15

16. Register File – Read Ports Chapter 4 — The Processor — 16 l Use two multiplexers whose control lines are the register numbers.

17. Register File – Write Port Chapter 4 — The Processor — 17 l We need 5-to-32 decoder in addition to the Write signal to generate actual write signal l The register data is common to all registers

18. Chapter 4 — The Processor — 18 Load/Store Instructions Read register operands Calculate address using 16-bit offset Use ALU, but sign-extend offset Load: Read memory and update register Store: Write register value to memory

19. Chapter 4 — The Processor — 19 Branch Instructions Read register operands Compare operands Use ALU, subtract and check Zero output Calculate target address Sign-extend displacement Shift left 2 places (word displacement) Add to PC + 4 Already calculated by instruction fetch

20. Chapter 4 — The Processor — 20 Branch Instructions Just re-routes wires Sign-bit wire replicated

21. Chapter 4 — The Processor — 21 Composing the Elements First-cut data path does an instruction in one clock cycle Each datapath element can only do one function at a time Hence, we need separate instruction and data memories Use multiplexers where alternate data sources are used for different instructions

22. Chapter 4 — The Processor — 22 R-Type/Load/Store Datapath

23. Chapter 4 — The Processor — 23 Full Datapath

24. Chapter 4 — The Processor — 24 ALU Control ALU used for Load/Store: F = add Branch: F = subtract R-type: F depends on funct field §4.4 A Simple Implementation Scheme ALU controlFunction 0000AND 0001OR 0010add 0110subtract 0111set-on-less-than 1100NOR

25. Chapter 4 — The Processor — 25 ALU Control Assume 2-bit ALUOp derived from opcode Combinational logic derives ALU control opcodeALUOpOperationfunctALU functionALU control lw00load wordXXXXXXadd0010 sw00store wordXXXXXXadd0010 beq01branch equalXXXXXXsubtract0110 R-type10add100000add0010 subtract100010subtract0110 AND100100AND0000 OR100101OR0001 set-on-less-than101010set-on-less-than0111

26. Chapter 4 — The Processor — 26 The Main Control Unit Control signals derived from instruction 0rsrtrdshamtfunct 31:265:025:2120:1615:1110:6 35 or 43rsrtaddress 31:2625:2120:1615:0 4rsrtaddress 31:2625:2120:1615:0 R-type Load/ Store Branch opcodealways read read, except for load write for R-type and load sign-extend and add

27. Chapter 4 — The Processor — 27 Datapath With Control

28. Chapter 4 — The Processor — 28 R-Type Instruction

29. Chapter 4 — The Processor — 29 Load Instruction

30. Chapter 4 — The Processor — 30 Branch-on-Equal Instruction

31. Control Unit The input is the Op field (6 bits) from the instruction register The output is 9 control signals Chapter 4 — The Processor — 31

32. Control Unit Chapter 4 — The Processor — 32

33. ALU Control The ALU control has two inputs: 1.ALUOp (2 bits) from the control unit 2.Funct field (6 bits) from the instruction register The ALU control has a 3-bit output FunctionBnegateOperation and000 or001 add010 sub110 slt111 Chapter 4 — The Processor — 33

34. ALU Control InstALUOpFunctBnegate Operation Operation and10100100000 or10100101001 add10100000010 sub10100010110 slt10101010111 lw00n/a010 sw00n/a010 beq01n/a110 Chapter 4 — The Processor — 34

35. Chapter 4 — The Processor — 35 Implementing Jumps Jump uses word address Update PC with concatenation of Top 4 bits of old PC 26-bit jump address 00 Need an extra control signal decoded from opcode 2address 31:2625:0 Jump

36. Chapter 4 — The Processor — 36 Datapath With Jumps Added

37. Chapter 4 — The Processor — 37 Performance Issues Longest delay determines clock period Critical path: load instruction Instruction memory  register file  ALU  data memory  register file Not feasible to vary period for different instructions Violates design principle Making the common case fast We will improve performance by pipelining

38. Multicycle Datapath Approach See the last set of slides. Chapter 4 — The Processor — 38

39. Chapter 4 — The Processor — 39 Pipelining Analogy Pipelined laundry: overlapping execution Parallelism improves performance §4.5 An Overview of Pipelining Four loads: Speedup = 8/3.5 = 2.3 Non-stop: Speedup = 2n/0.5n + 1.5 ≈ 4 = number of stages

40. Chapter 4 — The Processor — 40 MIPS Pipeline Five stages, one step per stage 1.IF: Instruction fetch from memory 2.ID: Instruction decode & register read 3.EX: Execute operation or calculate address 4.MEM: Access memory operand 5.WB: Write result back to register

41. Chapter 4 — The Processor — 41 Pipeline Performance Assume time for stages is 100ps for register read or write 200ps for other stages Compare pipelined datapath with single-cycle datapath InstrInstr fetchRegister read ALU opMemory access Register write Total time lw200ps100 ps200ps 100 ps800ps sw200ps100 ps200ps 700ps R-format200ps100 ps200ps100 ps600ps beq200ps100 ps200ps500ps

42. Chapter 4 — The Processor — 42 Pipeline Performance Single-cycle (T c = 800ps) Pipelined (T c = 200ps)

43. Chapter 4 — The Processor — 43 Pipeline Speedup If all stages are balanced i.e., all take the same time Time between instructions pipelined = Time between instructions nonpipelined Number of stages If not balanced, speedup is less Speedup due to increased throughput Latency (time for each instruction) does not decrease

44. Chapter 4 — The Processor — 44 Pipelining and ISA Design MIPS ISA designed for pipelining All instructions are 32-bits Easier to fetch and decode in one cycle c.f. x86: 1- to 17-byte instructions Few and regular instruction formats Can decode and read registers in one step Load/store addressing Can calculate address in 3 rd stage, access memory in 4 th stage Alignment of memory operands Memory access takes only one cycle

45. Chapter 4 — The Processor — 45 Hazards Situations that prevent starting the next instruction in the next cycle Structure hazards A required resource is busy Data hazard Need to wait for previous instruction to complete its data read/write Control hazard Deciding on control action depends on previous instruction

46. Chapter 4 — The Processor — 46 Structure Hazards Conflict for use of a resource In MIPS pipeline with a single memory Load/store requires data access Instruction fetch would have to stall for that cycle Would cause a pipeline “bubble” Hence, pipelined datapaths require separate instruction/data memories Or separate instruction/data caches

47. Chapter 4 — The Processor — 47 Data Hazards An instruction depends on completion of data access by a previous instruction add$s0, $t0, $t1 sub$t2, $s0, $t3

48. Chapter 4 — The Processor — 48 Forwarding (aka Bypassing) Use result when it is computed Don’t wait for it to be stored in a register Requires extra connections in the datapath

49. Chapter 4 — The Processor — 49 Control Hazards Branch determines flow of control Fetching next instruction depends on branch outcome Pipeline can’t always fetch correct instruction Still working on ID stage of branch In MIPS pipeline Need to compare registers and compute target early in the pipeline Add hardware to do it in ID stage

50. Chapter 4 — The Processor — 50 Stall on Branch Wait until branch outcome determined before fetching next instruction

51. Chapter 4 — The Processor — 51 Pipeline Summary Pipelining improves performance by increasing instruction throughput Executes multiple instructions in parallel Each instruction has the same latency Subject to hazards Structure, data, control Instruction set design affects complexity of pipeline implementation The BIG Picture

52. Chapter 4 — The Processor — 52 MIPS Pipelined Datapath §4.6 Pipelined Datapath and Control WB MEM Right-to-left flow leads to hazards

53. Chapter 4 — The Processor — 53 Pipeline registers Need registers between stages To hold information produced in previous cycle

54. Chapter 4 — The Processor — 54 Pipeline Operation Cycle-by-cycle flow of instructions through the pipelined datapath “Single-clock-cycle” pipeline diagram Shows pipeline usage in a single cycle Highlight resources used c.f. “multi-clock-cycle” diagram Graph of operation over time We’ll look at “single-clock-cycle” diagrams for load & store

55. Chapter 4 — The Processor — 55 IF for Load, Store, …

56. Chapter 4 — The Processor — 56 ID for Load, Store, …

57. Chapter 4 — The Processor — 57 EX for Load

58. Chapter 4 — The Processor — 58 MEM for Load

59. Chapter 4 — The Processor — 59 WB for Load Wrong register number

60. Chapter 4 — The Processor — 60 Corrected Datapath for Load

61. Chapter 4 — The Processor — 61 EX for Store

62. Chapter 4 — The Processor — 62 MEM for Store

63. Chapter 4 — The Processor — 63 WB for Store

64. Chapter 4 — The Processor — 64 Multi-Cycle Pipeline Diagram Form showing resource usage

65. Chapter 4 — The Processor — 65 Multi-Cycle Pipeline Diagram Traditional form

66. Chapter 4 — The Processor — 66 Single-Cycle Pipeline Diagram State of pipeline in a given cycle

67. Chapter 4 — The Processor — 67 Pipelined Control (Simplified)

68. Chapter 4 — The Processor — 68 Pipelined Control Control signals derived from instruction As in single-cycle implementation

69. Chapter 4 — The Processor — 69 Pipelined Control

70. Chapter 4 — The Processor — 70 Fallacies Pipelining is easy (!) The basic idea is easy The devil is in the details e.g., detecting data hazards Pipelining is independent of technology So why haven’t we always done pipelining? More transistors make more advanced techniques feasible Pipeline-related ISA design needs to take account of technology trends e.g., predicated instructions §4.14 Fallacies and Pitfalls

71. Chapter 4 — The Processor — 71 Pitfalls Poor ISA design can make pipelining harder e.g., complex instruction sets (VAX, IA-32) Significant overhead to make pipelining work IA-32 micro-op approach e.g., complex addressing modes Register update side effects, memory indirection e.g., delayed branches Advanced pipelines have long delay slots

72. Chapter 4 — The Processor — 72 Concluding Remarks ISA influences design of datapath and control Datapath and control influence design of ISA Pipelining improves instruction throughput using parallelism More instructions completed per second Latency for each instruction not reduced Hazards: structural, data, control §4.14 Concluding Remarks