1. EE415 VLSI Design

2. Read 4.1, 4.2 COMBINATIONAL LOGIC

3. EE415 VLSI Design Example Gate: COMPLEX CMOS GATE

4. EE415 VLSI Design Propagation Delay Analysis - The Switch Model

5. EE415 VLSI Design Analysis of Propagation Delay

6. EE415 VLSI Design What is the Value of R on ? Computing R on for t PHL, for an inverter

7. EE415 VLSI Design Numerical Examples of Resistances for 1.2  m CMOS See Example 4.2, table 3.3

8. EE415 VLSI Design Transistor Sizing V DD A B C D D A BC 1 2 2 2 6 6 12 F for symmetrical response (dc, ac) for performance Focus on worst-case Input Dependent Numbers indicate transistor sizing with minimum size equal to 1

9. EE415 VLSI Design Design for Worst Case V Additional geometry changes which compensate for the worst case path

10. EE415 VLSI Design Problems with Complementary CMOS Gate with N inputs requires 2N transistors other circuit styles use N+1 transistors t p deteriorates with high fan-in increases total capacitance series connected transistors slows down gate fan-out loads down gate 1 fan-out = 2 gate capacitors (PMOS and NMOS)

11. EE415 VLSI Design Influence of Fan-In and Fan-Out on Delay V DD A B A B C D CD t p a 1 FI a 2 FI 2 a 3 FO+ = Fan-Out: Number of Gates Connected 2 Gate Capacitances per Fan-Out FanIn:Quadratic Term due to: 1. Resistance Increasing 2. Capacitance Increasing (t pHL )

12. EE415 VLSI Design t p as a Function of Fan-In 13579 fan-in 0.0 1.0 2.0 3.0 4.0 t p ( n s e c ) t pHL t p t pLH linear quadratic AVOID LARGE FAN-IN GATES! (Typically than FI < 4) Gate: NAND fan-out = 1

13. EE415 VLSI Design As long as Fan-out Capacitance dominates Progressive Sizing: Can Reduce Delay by more than 30%! Example 4.3: no sizing: t pHL = 1.1 nsec with sizing: t pHL = 0.81 nsec Fast Complex Gate - Design Techniques

14. EE415 VLSI Design Fast Complex Gate - Design Techniques Transistor Ordering

15. EE415 VLSI Design Fast Complex Gate - Design Techniques Improved Logic Design

16. EE415 VLSI Design Fast Complex Gate - Design Techniques Buffering: Isolate Fan-in from Fan-out C L C L Read Example 4.5

17. EE415 VLSI Design Example: Full Adder

18. EE415 VLSI Design A Revised Adder Circuit

19. EE415 VLSI Design Ratioed Logic Goal: to reduce the number of devices over complementary CMOS

20. EE415 VLSI Design Ratioed Logic V DD V SS PDN In 1 2 3 F R L Load Resistive N transistors + Load V OH = V DD V OL = R DN R + R L Asymmetrical response Static power consumption t pLH = 0.69 R L C L V DD

21. EE415 VLSI Design Active Loads

22. EE415 VLSI Design Load Lines of Ratioed Gates

23. EE415 VLSI Design Pseudo-NMOS

24. EE415 VLSI Design Pseudo-NMOS NAND Gate V DD GND Out