1. Classification of Simulators Logic Simulators Emulator-basedSchematic-basedHDL-based Event-drivenCycle-basedGateSystem

2. Classification of Simulators HDL-basedHDL-based: Design and testbench described using HDL –Event-driven –Cycle-based Schematic-basedSchematic-based: Design is entered graphically using a schematic editor EmulatorsEmulators: Design is mapped into FPGA hardware for prototype simulation. Used to perform hardware/software co-simulation.

3. (Some) EDA Tools and Vendors Logic Simulation –Scirocco (VHDL)  Synopsys –Verilog-XL (Verilog)  Cadence Design Systems –Leapfrog (VHDL)  Cadence Design Systems –VCS (Verilog)  Chronologic (Synopsys) Cycle-based simulation –SpeedSim (VHDL)  Quickturn –PureSpeed (Verilog)  Viewlogic (Synopsys) –Cobra  Cadence Design Systems –Cyclone  Synopsys

4. Event-driven Simulation Event: change in logic value at a node, at a certain instant of time  (V,T) Event-driven: only considers active nodes –Efficient Performs both timing and functional verification –All nodes are visible –Glitches are detected Most heavily used and well-suited for all types of designs

5. Event-driven Simulation Event: change in logic value, at a certain instant of time  (V,T) 1 0 1 0 1 0 1 D=2 a b c Events: Input: b(1)=1 Output: none 1 0 1 0 1 0 1 D=2 a b c Events: Input: b(1)=1 Output: c(3)=0 3

6. Event-driven Simulation Uses a timewheel to manage the relationship between components TimewheelTimewheel = list of all events not processed yet, sorted in time (complete ordering) When event is generated, it is put in the appropriate point in the timewheel to ensure causality

7. Event-driven Simulation b(1)=1 d(5)=1 D=1 1 0 1 0 1 D=2 a b c d(5)=1 d 5 0 1 e 0 1 3 c(3)=0 d(5)=1 0 1 4 e(4)=0 6 e(6)=1

8. Cycle-based Simulation Take advantage of the fact that most digital designs are largely synchronous Synchronous circuit: state elements change value on active edge of clock Only boundary nodes are evaluated Internal Node Boundary Node LatchesLatches LatchesLatches

9. Cycle-based Simulation Compute steady-state response of the circuit –at each clock cycle –at each boundary node LatchesLatches LatchesLatches Internal Node

10. Cycle-based versus Event-driven Cycle-based:Cycle-based: –Only boundary nodes –No delay information Event-driven:Event-driven: –Each internal node –Need scheduling and functions may be evaluated multiple times Cycle-based is 10x-100x faster than event-driven (and less memory usage) Cycle-based does not detect glitches and setup/hold time violations, while event-driven does

11. Simulation: Perfomance vs Abstraction.001x SPICE Event-driven Simulator Cycle-based Simulator 1x10x Performance and Capacity Abstraction

12. Simulation Testplan Simulation –Write test vectors –Run simulation –Inspect results About test vectors – HDL code coverage

13. Digitaalsüsteemide verifitseerimise kursus13 Formal verification Symbolic simulation Can be applied in property checking...... Or in input space constraining

14. Digitaalsüsteemide verifitseerimise kursus14 Symbolic simulation Free variables (primary inputs, flip-flops) and internal variables. Considers relations between free variables, not the stimuli values. Good for verifying properties. Circuit unrolling for sequential circuits. Expressions will become complex! BDDS used in representing the expressions.

15. Digitaalsüsteemide verifitseerimise kursus15 Circuit unrolling: Symbolic simulation

16. Digitaalsüsteemide verifitseerimise kursus16 Var.1. cycle h gb 1 · c 1 kk1k1 f n j Var.2. cycle h gb 2 · c 2 k f n j Symbolic simulation

17. Digitaalsüsteemide verifitseerimise kursus17 Symbolic verification Symbolic simulation allows considering several stimuli simultaneously. Thus suitable for verifying properties (assertions) Properties may be time-limited (bound) or time-unlimited (unbound) Symbolic verification can be applied to the former

18. Digitaalsüsteemide verifitseerimise kursus18 Input Space Constraining Assign concrete values to some inputs and simulate Simplifies the expressions considerably A goal to verify partial functionality (functional partitioning) or to represent the environment In the extreme case, where all the variables have values, it will be equivalent to normal simulation

19. Digitaalsüsteemide verifitseerimise kursus19 Input Space Constraining Var.1. cycle h gb 1 · c 1 kk1k1 f n j Var.2. cycle h gb 2 · c 2 k f n j

20. Digitaalsüsteemide verifitseerimise kursus20 Input Space Constraining Var.1. cycle h0 gb 1 · c 1 kk 1 k 1 (b 1 · c 1 ) f n j Var.2. cycle h g0 k f n 1 j a 1 =1, c 2 =0

21. Digitaalsüsteemide verifitseerimise kursus21 Input Space Constraining

22. Digitaalsüsteemide verifitseerimise kursus22 Input Space Constraining Inputs x, y, z and outputs p, q x, y, z may hold values 100, 111, 010, 011 To constrain we encode by variables v, w We get x = ¬v, y = v+w, z = w (v, w)(x, y, z) 00100 01111 10010 11011