1. 33 rd IEEE International Conference on Computer Design ICCD 2015 33 rd IEEE International Conference on Computer Design ICCD 2015 Improving Memristor Memory with Sneak Current Sharing Manjunath Shevgoor, Rajeev Balasubramonian, Naveen Muralimanohar, Yoocharn Jeon University of Utah, HP Labs Improving Memristor Memory with Sneak Current Sharing 1

2. 33 rd IEEE International Conference on Computer Design ICCD 2015 Background  Store data in the form of resistance  Metal oxide sandwiched between two electrodes  Inherently non conducting  Creation of conductive Filaments of oxygen vacancies reduces resistance Improving Memristor Memory with Sneak Current Sharing 2 Source: Cong Xu et al., Modeling and Design Analysis of 3D Vertical Resistive Memory - A Low Cost Cross-Point Architecture, ASPDAC 2014

3. 33 rd IEEE International Conference on Computer Design ICCD 2015 Voltage Dependent Resistance  R(V/p) and R(V ) are the equivalent resistance of the cell biased at V/p and V  Kr is the non-linearity.  Eg: if Kr=20, resistance increases 10x when voltage is halved  Resistance decreases with increasing voltage Improving Memristor Memory with Sneak Current Sharing 3 The resistance of a ReRAM cell is not constant but varies with the applied voltage Kr(p, V ) = p * R(V/p)/R(V )

4. 33 rd IEEE International Conference on Computer Design ICCD 2015 Improving Memristor Memory with Sneak Current Sharing 4 Bit Line Word Line DRAM Cell Bit Line Word Line PCM Cell Word Line Bit Line Memristor Cell Cell Size of 4F 2

5. 33 rd IEEE International Conference on Computer Design ICCD 2015 Cross Point Structure Improving Memristor Memory with Sneak Current Sharing 5 Non-linearity makes it possible to select a cell without an access transistor. Arrays can be layered vertically without resorting to 3D stacking. Mem- ristor Selector Memristor Cell

6. 33 rd IEEE International Conference on Computer Design ICCD 2015 Reading and Writing Improving Memristor Memory with Sneak Current Sharing 6 Half Selected Cells Selected Cell Sneak Current 0V Vdd/2 Vdd

7. 33 rd IEEE International Conference on Computer Design ICCD 2015 Improving Memristor Memory with Sneak Current Sharing 7 RWRW RWRW RWRW RWRW RWRW RWRW RWRW RWRW RWRW RWRW RWRW RWRW 0 V/2 V Bit Lines Word Lines V W1 V W2 V WN V WN1 V WNM Bit Line Mux Bit line and word line resistances eat into the cell Voltage

8. 33 rd IEEE International Conference on Computer Design ICCD 2015 EFFECTS OF I LEAK Improving Memristor Memory with Sneak Current Sharing 8

9. 33 rd IEEE International Conference on Computer Design ICCD 2015 Effects of I leak Improving Memristor Memory with Sneak Current Sharing 9 Decreases Voltage at selected cell  Increases Write Latency  Can cause Write Failure Distorts bit line current  Increases read complexity  Decreases read margin Limits Array Size

10. 33 rd IEEE International Conference on Computer Design ICCD 2015 Impact on Writes Improving Memristor Memory with Sneak Current Sharing 10 Bit Line Mux Word Line Drivers  Longer write latencies  Increased error rates

11. 33 rd IEEE International Conference on Computer Design ICCD 2015 Impact on Reads Improving Memristor Memory with Sneak Current Sharing 11 V read 0 I read I leak V read /2 Sneak path currents can distort I read

12. 33 rd IEEE International Conference on Computer Design ICCD 2015 Improving Memristor Memory with Sneak Current Sharing 12 Read Step 1: Read background current (I leak ) V read /2 0 I leak V read /2

13. 33 rd IEEE International Conference on Computer Design ICCD 2015 13 Read Step 2: Read total V read current (I read ) V read 0 I read I leak V read /2 Improving Memristor Memory with Sneak Current Sharing

14. 33 rd IEEE International Conference on Computer Design ICCD 2015 Improving Memristor Memory with Sneak Current Sharing 14 State of selected cell determines I read ~ I leak tBG_READtREAD Read Latency

15. 33 rd IEEE International Conference on Computer Design ICCD 2015 Improving Memristor Memory with Sneak Current Sharing 15 Proposal : Re-use value in sample and hold circuit V read V read /2 VrVr P acc P prech S1 Sensing Circuit S2 Sample and Hold Sneak Current

16. 33 rd IEEE International Conference on Computer Design ICCD 2015 Reusing Sneak Current Read 16 Sneak Current uA Columns Improving Memristor Memory with Sneak Current Sharing Rows

17. 33 rd IEEE International Conference on Computer Design ICCD 2015 Improving Memristor Memory with Sneak Current Sharing 17 Re-Use Sneak Current Reading for the same Column tBG_READtREAD Read Latency1 tREAD Read Latency2

18. 33 rd IEEE International Conference on Computer Design ICCD 2015 Trading off locality for parallelism Memristor architecture has 32 sub-banks in each bank Mapping successive cache lines to same sub-bank limits parallelism Address Mapping Schemes Improving Memristor Memory with Sneak Current Sharing 18 32 ReuseMap entire page to a Column 4 ReuseMap 4 successive cache lines to same sub-bank 4 InterleaveMap every 4 th cache line to same sub-bank 32 InterleaveMap every 32 nd cache line to same sub-bank XOR Map successive cache line to Channel: Rank: Bank: Sub-bank; XOR sub-bank with Column

19. 33 rd IEEE International Conference on Computer Design ICCD 2015 Methodology Processor Model 8 Core 000 model using Simics 32KB L1 cache, 8MB L2 cache Evaluated on SPEC2006 workloads Memory Model 2 Channel, 2 Ranks, 8 Banks, 32 sub-banks 1600 Mbps channel Improving Memristor Memory with Sneak Current Sharing 19

20. 33 rd IEEE International Conference on Computer Design ICCD 2015 Performance Vs Baseline Improving Memristor Memory with Sneak Current Sharing 20

21. 33 rd IEEE International Conference on Computer Design ICCD 2015 Memory Latency Improving Memristor Memory with Sneak Current Sharing 21

22. 33 rd IEEE International Conference on Computer Design ICCD 2015 Column Hit Rate Improving Memristor Memory with Sneak Current Sharing 22

23. 33 rd IEEE International Conference on Computer Design ICCD 2015 Exploring Address Mapping Improving Memristor Memory with Sneak Current Sharing 23

24. 33 rd IEEE International Conference on Computer Design ICCD 2015 Read Power Improving Memristor Memory with Sneak Current Sharing 24

25. 33 rd IEEE International Conference on Computer Design ICCD 2015 Conclusions  With great density come a few challenges  Sneak Currents limit array size, complicate reads, and delay writes  Affect reliability  Background current can be reused  Performance increase of 8.3%  Read Latency reduce by 20%  Memristor Power reduced by 25.8%  Explored locality/parallelism trade off 25 Improving Memristor Memory with Sneak Current Sharing

26. 33 rd IEEE International Conference on Computer Design ICCD 2015 THANK YOU Improving Memristor Memory with Sneak Current Sharing 26