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Oct. 2007, Wu Jinyuan, FermilabIEEE NSS Refresher Course1 Digital Design with FPGAs: Examples and Resource Saving Tips Screen B Wu, Jinyuan Fermilab IEEE.

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Presentation on theme: "Oct. 2007, Wu Jinyuan, FermilabIEEE NSS Refresher Course1 Digital Design with FPGAs: Examples and Resource Saving Tips Screen B Wu, Jinyuan Fermilab IEEE."— Presentation transcript:

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2 Oct. 2007, Wu Jinyuan, FermilabIEEE NSS Refresher Course1 Digital Design with FPGAs: Examples and Resource Saving Tips Screen B Wu, Jinyuan Fermilab IEEE NSS 2007 Refresher Course Oct, 2007

3 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 2 Indirect Cost of Complexity If something like this can do the job… … why do these?

4 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 3 Outline Digital Design with FPGAs (This 45 min. Course)  Logic Element in a Nutshell  Variations of the Registered Adders  Tricks of Using RAM  RAM based histograms  Topics on Multipliers  Curved Track Fitter Advanced Topics on FPGA Applications (Included as Supplemental Materials)  Doublet Finding, Hash Sorter  Triplet Finding, Tiny Triplet Finder (TTF)  Options of Sequence Control, Recursive Structure, etc.

5 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 4 What Can Be Done With a Logic Element “Any” 4-in Functions Full Adder CI A B S CO DQ DQ DQ DQ ABCDABCD

6 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 5 Xilinx Look-Up Table DQ ENA CLRN LUT4 SRL16 RAM16 4-input Look-Up Table 16-bit Shift Register 16-bit Distributed RAM

7 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 6 Transistor Usage of Logic Element DQ ENA CLRN LUT 16-bit 6-transistor RAM bit At least 96 transistors X 16

8 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 7 Full Adder DQ ENA CLRN LUT 8-bit LUT 8-bit Full Adder CI A B S CO DQ At least 96 transistors

9 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 8 Transistor Counts FPGA 1LE: 4-in LUT + DFF>96 4-input NAND, NOR etc.8 2-to-1 MUX6 Static RAM6/bit Full Adder24-28 N-bit Multiplier> (N 2 )/2 FA

10 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 9 TDC Using FPGA Logic Chain Delay This scheme uses current FPGA technology Low cost chip family can be used. (e.g. EP1K10QC208-2 $15.25) Fine TDC precision can be implemented in slow devices (e.g., 0.4 ns in a 200 MHz chip). IN CLK

11 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 10 Edge Detection + Sample Selection

12 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 11 ADC Test: Waveform Digitization on BD3_19 Raw Data Input Waveform, Overlap Trigger & Reference Voltage Converted FPGA TDC 50 1000pF 100 V REF

13 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 12 Sorter Operation Operation: 1. Initialization: All registers become 0xFF after DUMP=1 for at least 4 clock cycles. 2. Data Fetching: All data are clocked through and lowest four numbers are stored. 3. Dump: The lowest four numbers are output in sequence and all registers become 0xFF, i.e., initialized. Warning: To keep all sorted data, do not use this circuit. Consider other schemes. 8312314728716555234691197216448712231916 Sorter

14 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 13 Outline Digital Design with FPGAs (This 45 min. Course)  Logic Element in a Nutshell  Variations of the Registered Adders  Tricks of Using RAM  RAM based histograms  Topics on Multipliers  Curved Track Fitter Advanced Topics on FPGA Applications (Included as Supplemental Materials)  Doublet Finding, Hash Sorter  Triplet Finding, Tiny Triplet Finder (TTF)  Options of Sequence Control, Recursive Structure, etc.

15 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 14 LE Implementation of Registered Adder DQ ENA CLRN LUT 8-bit LUT 8-bit DQ ENA CLRN LUT 8-bit LUT 8-bit A1A1 B1B1 A2A2 B2B2

16 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 15 The Counter With Inc, Dec and Count Enable Controls, a Special Case of Accumulator D[]Q[] 0/+1/-1 B[] A+B D[] EN Q[] SLOAD D[] SCLR Inc/Dec CNTEN EN Don’t confuse the count enable CNTEN With clock enable EN. 0: Disable +1: Inc -1: Dec

17 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 16 Decimations: With Integer ratios f S f D = f S / 6 Sample Interval = 6

18 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 17 Resource Usage of Comparators == A[] B[] LUT4 A A B LUT 8-bit LUT 8-bit LUT 8-bit LUT 8-bit A>B A[] B[] A B A B A B LUT4 Equality Comparator A==Constant 0.25 LE/bit + Equality Comparator A==B 0.5 LE/bit + Magnitude Comparator A>B 1 LE/bit

19 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 18 Decimation With Non-integer ratios f S f D = f S / 6 f D = f S / 6.2 Sample Interval = 6 Sample Interval = 7

20 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 19 Duty-Cycle Based Single-Pin DAC Counter Q A B A>B DAC Input The duty-cycle of the comparator output is proportional to the DAC input at port A. Use external RC as low-pass filter. Output voltage of an ideal LP filter is proportional to the DAC input.

21 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 20 Exponential Sequence Generator  Q SET D if (CO==1) {Q = Q - Q/32;} An exponential sequence is generated using an accumulator shown above. Note that not even one multiplier is used. Other function sequences: sine, co-sine, tangent, co- tangent etc. can also be generated similarly.

22 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 21 Outline Digital Design with FPGAs (This 45 min. Course)  Logic Element in a Nutshell  Variations of the Registered Adders  Tricks of Using RAM  RAM based histograms  Topics on Multipliers  Curved Track Fitter Advanced Topics on FPGA Applications (Included as Supplemental Materials)  Doublet Finding, Hash Sorter  Triplet Finding, Tiny Triplet Finder (TTF)  Options of Sequence Control, Recursive Structure, etc.

23 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 22 CNT -L RAM Q RA RE D WA WE D Q CNT RAM Q RA RE D WA WE CNT PUSHPOP D Q PUSH Implementation of Pipeline and FIFO

24 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 23 TDC TS DV TS CM T FIFO PUSH OUT Zero-Suppression

25 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 24 Pipeline and FIFO

26 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 25 TDC Data Concentration 48 Ch L1 Buffer 1xM4K 16x256 Zero Supp. TDC/HRL EV Buffer & Truncating 16x128x2 TDC/HRL Ch 4-7, TDC & L1 Buffer TDC/L1 Buffer/MUX Channels 16-31 TDC/L1 Buffer/MUX Channels 32-47 Ch 8-11, TDC & L1 Buffer Ch 12-15, TDC & L1 Buffer

27 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 26 Ping-Pong Paged RAM MPU CNT RAM QA QB DA AA WEA DB AB WEB UPDATA FA P MA !P FA P MA AA[9]=!P AB[9]=P FA MA P==0  MPU accesses page 0  FPGA accesses page 1 P==1  MPU accesses page 1  FPGA accesses page 0

28 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 27 FPGA RAM Aspect Ratio

29 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 28 Each Address Line: Doubles RAM Size. 256 Words 256 Words 256 Words 256 Words 256 Words 8 address lines 9 address lines 8+8 address lines

30 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 29 High Precision 2^N LUT 2 (A+B+C) = 2 (A) * 2 (B) *(1+(ln2)*C) X AB ROM LUT 2 8 =256 w ROM LUT 2 8 =256 w C 2 (A) 2 (B) X 1+ (32-bit Precision) X 0.6931471 Constant Multiplication, May use LUT

31 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 30 Outline Digital Design with FPGAs (This 45 min. Course)  Logic Element in a Nutshell  Variations of the Registered Adders  Tricks of Using RAM  RAM based histograms  Topics on Multipliers  Curved Track Fitter Advanced Topics on FPGA Applications (Included as Supplemental Materials)  Doublet Finding, Hash Sorter  Triplet Finding, Tiny Triplet Finder (TTF)  Options of Sequence Control, Recursive Structure, etc.

32 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 31 Histogram Booking +1 RA,WA K

33 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 32 Read-After-Write (RAW) Hazard D Q K4 DV RAM QD WA WE RA D Q +1 D Q K1 K0K2 N1 Wrong! Wanted to be N1+1 K0K1K2K1K4 K0K1K2K1K4 K0K1K2K1K4 K0K1K2K1K4 N0N1N2N1N4 K0K1K2K1K4 N0+1N1+1N2+1N1+1N4+1

34 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 33 RAW Hazard Prevention: Instruction Merging D Q K DV RAM QD WA WE RA D Q +1+N D Q &&== If a bin is hit several times, they are combined in a single accumulation instruction. K1==K2 DV1 DV2 K1K2

35 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 34 Histogram Fast Reset Keep a run counter RC that ++ for each reset. Assign an Index RAM that has same number of bins as the Content RAM. When a bin is hit, the Index RAM is first readout (to MR) and then written with current RC. If MR!=RC, the bin is to be reset. If MR==RC, the bin is to be +1. +1 RA,WA K RC CE == 0 MR!=RC Old run MR==RC Current run Index RAM Reset Content RAM MR

36 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 35 Prevent Index RAM from Rolling Over The RC/Index RAM have limited bits that may cause roll-over (millennium-bug). E.g. RC=1, =513, =1025 look same with 9-bit RC. To prevent roll-over, write a bin of Index RAM with RC in rotational address at each reset. For a 256-bin histogram, the contents in Index RAM will be always RC-256 or newer. +1 RA,WA K RC CE == 0 MR!=RC Old run MR==RC Current run Index RAM Reset Content RAM MR A(RC)

37 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 36 Outline Digital Design with FPGAs (This 45 min. Course)  Logic Element in a Nutshell  Variations of the Registered Adders  Tricks of Using RAM  RAM based histograms  Topics on Multipliers  Curved Track Fitter Advanced Topics on FPGA Applications (Included as Supplemental Materials)  Doublet Finding, Hash Sorter  Triplet Finding, Tiny Triplet Finder (TTF)  Options of Sequence Control, Recursive Structure, etc.

38 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 37 Multipliers in Cyclone II Multiplier 18-bit x 18-bit

39 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 38 Approximation is OK X 8-bit Square |Y-X|<0.5 INT(Y+0.5)=X X2X2 00FF00&X 2 Y ^2 & sqrt X=256-511

40 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 39 Replacing Multiplication With Addition 00A A +) 5*A 00A A -) 248*A 000000 000

41 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 40 Outline Digital Design with FPGAs (This 45 min. Course)  Logic Element in a Nutshell  Variations of the Registered Adders  Tricks of Using RAM  RAM based histograms  Topics on Multipliers  Curved Track Fitter Advanced Topics on FPGA Applications (Included as Supplemental Materials)  Doublet Finding, Hash Sorter  Triplet Finding, Tiny Triplet Finder (TTF)  Options of Sequence Control, Recursive Structure, etc.

42 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 41 Relative Errors of Several Track Fitter Schemes Least Square Fitter Multiplier-less FPGA LS Fitter

43 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 42 Coefficient Table, Least Square Fitter Half-length of the Track z-z 0 16141210864 eiei e[i]eiei eiei eiei eiei eiei eiei -165.36 -143.327.58 -121.624.3411.312 -100.101.625.6517.918 -8-1.10-0.7-21.017.2731.031 -6-2.0-3-2.4-2-2.6-4-1.27.8861.056 -4-2.6-3-3.6-5-5.1-5-7.2-8-8.9-90.012146.3144 -2-3.0-3-4.4-4-6.6-5-10.7-9-18.8-20-36.6-40-73.1-64 0-3.2-2-4.6-2-7.2-8-11.9-14-22.2-20-48.8-56-146.3-160 2-3.0-3-4.4-4-6.6-5-10.7-9-18.8-20-36.6-40-73.1-64 4-2.6-3-3.6-5-5.1-5-7.2-8-8.9-90.012146.3144 6-2.0-3-2.4-2-2.6-4-1.27.8861.056 8-1.10-0.7-21.017.2731.031 100.101.625.6517.918 121.624.3411.312 143.327.58 165.36 Error2.913.023.053.153.223.263.413.433.65 3.933.994.284.29 Ratio 1.04 1.03 1.01 1.00 1.02 1.00

44 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 43 Coefficient Table, ML Fitter Half-length of the Track z-z 0 16141210864 eiei e[i]eiei eiei eiei eiei eiei eiei -165.36 -143.327.58 -121.624.3411.312 -100.101.625.6517.918 -8-1.10-0.7-21.017.2731.031 -6-2.0-3-2.4-2-2.6-4-1.27.8861.056 -4-2.6-3-3.6-5-5.1-5-7.2-8-8.9-90.012146.3144 -2-3.0-3-4.4-4-6.6-5-10.7-9-18.8-20-36.6-40-73.1-64 0-3.2-2-4.6-2-7.2-8-11.9-14-22.2-20-48.8-56-146.3-160 2-3.0-3-4.4-4-6.6-5-10.7-9-18.8-20-36.6-40-73.1-64 4-2.6-3-3.6-5-5.1-5-7.2-8-8.9-90.012146.3144 6-2.0-3-2.4-2-2.6-4-1.27.8861.056 8-1.10-0.7-21.017.2731.031 100.101.625.6517.918 121.624.3411.312 143.327.58 165.36 Error2.913.023.053.153.223.263.413.433.65 3.933.994.284.29 Ratio 1.04 1.03 1.01 1.00 1.02 1.00

45 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 44 Fitting Errors From Approximations 20% approximation in coefficients … …increases fitting error by only 2%.

46 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course 45 Additional Courses on FPGA Applications Digital Design with FPGAs (This 45 min. Course)  Logic Element in a Nutshell  Variations of the Registered Adders  Tricks of Using RAM  RAM based histograms  Topics on Multipliers  Curved Track Fitter Advanced Topics on FPGA Applications (Included as Supplemental Materials)  Doublet Finding, Hash Sorter  Triplet Finding, Tiny Triplet Finder (TTF)  Options of Sequence Control, Recursive Structure, etc. Reconfigurable Computing with FPGA (Planned)

47 Oct. 2007, Wu Jinyuan, FermilabIEEE NSS Refresher Course46 The End Thank you

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