1. Virtual Memory From course notes 0657.201 University of Waikato. Some material by Tony McGregor tonym@cs.waikato.ac.nz Other material from: The Architecture of Computer Hardware and Systems Software: An Information Technology Approach Irv Englander, John Wiley and Sons (WIE) ISBN: 0471310379 and Operating System Concepts, Peterson and Silberschatz, Addison Wesley, ISBN 0-201- 06097-3. Chapter 5. also Drawings and notes by me Richard Jones – richard@ib-computing.com

2. Virtual (logical) Memory The user program sees memory as contiguous. The actual program is spread throughout physical memory. Hardware translates logical address references to physical addresses – effectively “relocating” code dynamically.

3. Paging The logical address space is divided into relatively small, fixed size pages. Physical memory is divided into the same sized units (frames). Hardware translates pages to frames. address translation virtual address space of process 1 virtual address space of process 2 physical memory

4. Pages and frames 01 14 23 37 see, Peterson and Silberschatz, p160 and Englander, p540 page 0 page 1 page 2 page 3 logical memory page table 0 1page 0 2 3page 2 4page 1 5 6 7page 3 physical memory frame number page/frame sizes are determined by the hardware.

5. Page number and offset The MMU splits (logical) addresses into a page number and an offset within the page. 20-bit address 10010101101001010010 page numberoffset

6. Page table 3D7A1 2D 2E 3A 3D2F357 3E 41 page table 2F3577A1 page offset 2F3577A0 2F3577A1 2F3577A2 physical memory Englander p 540

7. Features of paging Logical and physical addresses do not have to be the same size. There is no external fragmentation – any free memory frame can be allocated to a process. Internal fragmentation still occurs if a program does not end exactly on a page boundary.

8. Virtual vs Physical Memory 02 17 25 34 4 5 6 7 0z 1y 2x 3w 4v 5u 6t 7s 8r 9q Ap Bo 00a 01b 02c 10d 11e 12f 20g 21h 22I 30j 31k 32l 10 20 30 40 50 60 07 08 09 10 11 12 13 14 15 base

9. Disadvantage of paging Since the logical address must be converted to a physical address using table lookup, access to memory is slowed by a factor of 2. Various schemes are incorporated in the hardware to speed access – eg use of high-speed cache to store recently “hit” pages.

10. Where are they? 3D7A1 2D 2E 3A 3D2F357 3E 41 2F3577A1 page offset In this example, it is apparent that some pages are not in the page table. Where are they? What do we need to do if this happens?

11. Swap files Primary memory is limited in size. Pages can be held on secondary memory. If the CPU tries to execute an instruction or use data on a page that is not in the page table a page fault (interrupt) is generated.

12. Page fault 30F 310 311load 3D7A1 312 313 314 2F 30 32 3F 40 42 page table no page found page 3D located and loaded in page table updated possibly an existing page is removed and stored instruction executed

13. Page swapping Most programs only access a small percentage of their memory space during any particular time of their execution. The associated pages can be identified as a working set. Some systems dynamically adjust the size of the working set by tracking page faults for each process.

14. Thrashing Pages are regularly being swapped in and out as processes execute. This is slow compared to CPU clock time. Sometimes pages of one process are replaced by another. As the CPU switches between processes it can generate a huge number of page faults slowing the system dramatically.

15. Thrashing process B process A process Dprocess C address translation memory frames swap disk switch to process B, not many pages in memory, load them in. switch to process C

16. Segmentation Segments are larger units of memory than pages – represent another approach. They are normally constructed by the compiler/assembler. They can be swapped as a unit if thrashing occurs. Segments can be tagged, indicating the type of data held.

17. Segments subroutine xyz function sqrt Operating System Concepts, Peterson and Silberschatz, Addison Wesley, isbn 0-201-06097-3, p160 stack symbol table main program logical address space segment table limitbase 10001400 4006300 4004300 11003200 10004700 1400 2400 3200 4300 4700 5700 6300 6700 segment 0 segment 3 segment 2 segment 4 segment 1 physical memory

18. Segments Segments can be a unit of memory protection – causing segmentation faults. Segments (like code/.text) can be marked as read-only. Segments can be shared among processes.

19. Unix executables.text.data.bss Relocation table Symbol table tagged as read only (could be shared) (initialised) copied into their own segments (un- initialised) space is allocated stack segment

20. Paged segmentation Combination of segmentation and paging. Segment table can be extended to include ownership and access bits. Shared segments will have segment tables (in each shared process) which point to the same page table, access bits might be different.

21. Paged segmentation 3D7A1 2D 2E 3A 3D4A 3E 41 Segment table - pointer to page table (1 segment table per process) 2F377A1 segment offset 2F377A0 2F377A1frame 2F377A2 physical memory 7A1 page offset Physical address 1 3 4 72F377 9 A Page table 4A - pointer to base physical address (1 page table per segment)

22. Paged segmentation In this scheme, as with ordinary segmentation, a.text (or code) segment can be shared between different processes. Each process has different data tables. compiler source code physical memory compiler source code segment table A page tables A page tables B process A process B segment table B

23. Segmented paging Alternative scheme (not common). Segment table with fixed number of entries. Each entry points to the base of a page table. Page table entry plus offset in logical address gives memory location.

24. Segmented paging 73A1 1 3 4 74A 9 A Segment table - pointer to base in page table 2F377A1 page offset 2F377A0 2F377A1frame 2F377A2 physical memory 3 offset in page table Physical address 4A 4C 4D 4E2F377 4F 51 (part of) Page table

25. Conclusion Memory management systems are constrained by the hardware. Logical addresses mapped to physical addresses – inefficient to do in software. Any of the schemes can include swapping to cater for more jobs than physical memory permits.