1. 9/20/6Lecture 3 - Instruction Set - Al1 Exception Handling

2. 9/20/6Lecture 3 - Instruction Set - Al2 Exception Handling  Interrupts and Exceptions  An introduction  Classes and Mechanisms

3. 9/20/6Lecture 3 - Instruction Set - Al3 Interrupts and Exceptions  Topics are closely related Facilities to handle both are near identical or the same  Interrupt – physical assertion of a pin(s) to attain processors attention  Exception – an event that alters the normal execution of a program Combines software and hardware aspects of a processor

4. 9/20/6Lecture 3 - Instruction Set - Al4 Exception Handling  Bridge three components of microprocessor Hardware Software Operating System  In reality an exception is a call to the OS  Features common to a subroutine call and may be explicit

5. 9/20/6Lecture 3 - Instruction Set - Al5 Exceptions  Can be divided into two classes Internal exceptions – those generated by execution of an instruction External exceptions – those caused by actions taken outside the processor chip  Each class/subclass is handled by its own exception handler – software that is part of OS and responds to the exception

6. 9/20/6Lecture 3 - Instruction Set - Al6 Exceptions  Subroutine calls by a program are synchronous  Exceptions (majority) are asynchronous  Polling versus exception Polling – periodically check for a condition or input Typically poll until event occurs – busy waiting

7. 9/20/6Lecture 3 - Instruction Set - Al7 Exceptions  Alternative is to do useful processing until an event occurs (asynchronously) and then “service” the event  Interrupt latency – the time from the interrupt occurring (interrupt request) and the processor responding

8. 9/20/6Lecture 3 - Instruction Set - Al8 A typical sequence of actions  Interrupt (exception) asserted  Complete current instruction  Save Program Counter (PC) – this would go on the supervisory stack in the 68000  Save the state of the processor Stack the registers  Jump to interrupt (exception) service routine

9. 9/20/6Lecture 3 - Instruction Set - Al9 Return from interrupt  Complete interrupt (exception) processing  Restore registers  Restore program counter  Occurrence of interrupt (exception) is totally transparent to process executing at time of interrupt (exception)

10. 9/20/6Lecture 3 - Instruction Set - Al10 Nonmaskable interrupt  Interrupts are “requests” Requests can be serviced, denied or deferred  Nonmaskabel interrupts (NMI) are those that cannot be denied or deferred  Examples Low-voltage interrupt detector – response would be to perform orderly shutdown High temperature detector

11. 9/20/6Lecture 3 - Instruction Set - Al11 Prioritized Interrupt  More than one level of interrupt possible  Prioritize High level – serviced sooner  Example – disk service routine to capture and transfer the data from the disk Medium level – serviced in acceptable time  Example – keyboard where data may be held for 200ms Low level – serviced as processing allows  Example – continue adding data to printer output buffer

12. 9/20/6Lecture 3 - Instruction Set - Al12 Vectored Interrupts  Identify the requesting device  8-bit processors – typically only have an IRQ* pin and input Interrupt Service routine must “poll” the devices capable of asserting interrupt to determine who

13. 9/20/6Lecture 3 - Instruction Set - Al13 Vectored Interrupts (2)  IACK – output pin on processor When asserted, requesting device places identification code (number) on bus Processor (in supervisory mode) branches to correct routine to service peripheral  68000 has both vectored and non-vectored interrupts

14. 9/20/6Lecture 3 - Instruction Set - Al14 Exceptions  Roots in the days of mainframes  “Deviation in normal sequence of actions”  Interrupts are asynchronous exception  Hardware error exceptions Trying to read from a memory address not populated  Software exceptions Error – Ex: Illegal op code Deliberate – Termed a TRAP – can be used to “create new instructions” – Ex: floating point addition

15. 9/20/6Lecture 3 - Instruction Set - Al15 Quick example  68000 has and exception vector tabel In memory – each exception has an associated entry in the table Entries are longwords (32 bits) Processor executes an indirect jump to the routine at that address stacking processor state RTE retrieves info and restores state

16. 9/20/6Lecture 3 - Instruction Set - Al16 Pseudocode for exception processing  What happens when an exception occurs

17. 9/20/6Lecture 3 - Instruction Set - Al17 The handler or Service routine

18. 9/20/6Lecture 3 - Instruction Set - Al18 An example Setting up being able to use serial peripheral (6850 ACIA) and its handler